PLL502-30 Datasheet, PDF (7/8 Pages) PhaseLink Corporation – 750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)

PLL502-30
750kHz – 800MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
PAD ASSIGNMENT
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
GND
GND
GND
GND
GND
N/C
GND
GNDBUF
OE_SELECT
LVDS
PECL
VDDBUF
VDDBUF
PECLB
LVDSB
CMOS
GNDBUF
OUTSEL1
SEL1
SEL0
VDD
VDD
VDD
VDD
OUTSEL0
XIN
XOUT
SEL3
SEL2
OE_CTRL
VCON
X (µm)
248
361
473
587
702
874
1042
1171
1400
1400
1400
1400
1400
1400
1400
1400
1389
1232
1042
854
659
559
459
358
194
109
109
109
109
109
109
Y (µm)
Description
109
109
109
109
109
109
109
109
125
259
476
616
716
871
1089
1227
1365
1365
1365
1365
1365
1365
1365
1365
1365
1223
1017
858
646
397
181
Ground.
Ground.
Ground.
Ground.
Ground.
No Connection.
Ground.
Ground, buffer circuitry.
Used to select between PECL or CMOS logic states for OE.
Internal pull up.
LVDS Output.
PECL Output.
3.3V power supply, Buffer circuitry.
3.3V power supply, Buffer circuitry.
Complementary PECL Output.
Complementary LVDS Output.
CMOS Output.
Ground, buffer circuitry.
Used to select CMOS, PECL or LVDS output type. Internal pull
up.
Used to select multiplication factor. Internal pull up.
Used to select multiplication factor. Internal pull up.
3.3V power supply.
3.3V power supply.
3.3V power supply.
3.3V power supply.
Used to select CMOS, PECL or LVDS output type. Internal pull
up.
Crystal input. See crystal specification page 3.
Crystal output. See crystal specification page 3.
Used to select multiplication factor. Internal pull up.
Used to select multiplication factor. Internal pull up.
Used to enable/disable the output(s). See Output Selection and
Enable table on page 1.
Voltage Control Input. 0V to 3.3V.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 01/20/06 Page 7