PLL502-30 Datasheet, PDF (1/8 Pages) PhaseLink Corporation – 750kHz - 800MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)

PLL502-30
750kHz – 800MHz Low Phase Noise VCXO (for 12 – 25MHz Crystals)
FEATURES
• 750kHz to 800MHz output range.
• Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
• Selectable CMOS, PECL and LVDS output.
• Selectable High Drive or Standard CMOS.
• 12 to 25MHz crystal input.
• No external load capacitor or varicap required.
• Output Enable selector.
• Wide pull range (+/-200ppm)
• 3.3V operation.
• Available in DIE (65 mil x 62 mil).
DESCRIPTION
The PLL502-30 is a monolithic low jitter and low
phase noise (-142dBc/Hz @ 10kHz offset) VCXO IC
Die, with CMOS, LVDS and PECL output, covering
the 750kHz to 800MHz output range. It allows the
control of the output frequency with an input voltage
(VCON), using a low cost crystal.
The same die can be used as a VCXO with output
frequencies ranging from F_XIN / 16 to F_XIN x 32
thanks to frequency selector pads. This makes the
PLL502-30 ideal as a universal die for applications
ranging from ADSL to SONET.
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
SEL
XIN
XOUT
Reference
Divider
XTAL
OSC
VARICAP
VCO
Divider
Phase
Detector
Charge
Pump
+
Loop
Filter
VCO
OE
CLKBAR
CLK
DIE CONFIGURATION
65 mil
(1550,1475)
25
24 23 22 21
20
19
18
17 GNDBUF
XIN 26
XOUT 27
Die ID:
A0505-18
16 CMOS
15 LVDSB
SEL3^ 28
14 PECLB
SEL2^ 29
13 VDDBUF
12 VDDBUF
OE_CTRL 30
C502A
11 PECL
10 LVDS
VCON 31
9 OE_SEL^
12345
6
78
Y
X
(0,0)
Note: ^ denotes internal pull up
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
0
0
1
1
OUTSEL0
(Pad #25)
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
PECL
LVDS
OE_SELECT
(Pad #9)
0
1 (Default)
OE_CTRL
(Pad #30)
0
(Default)
1
0
1
(Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OE_SELECT is “0”
Logical states defined by CMOS levels if OE_SELECT is “1”
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 01/20/06 Page 1