PL580-35 Datasheet, PDF (7/10 Pages) PhaseLink Corporation – 38MHz-320MHz Low Phase Noise VCXO

(Preliminary) PL580-35/37/38/39
38MHz-320MHz Low Phase Noise VCXO
10. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
CONDITIONS
RL = 50 Ω to (VDD – 2V)
(see figure)
MIN.
VDD – 1.025
MAX.
VDD – 1.620
UNITS
V
V
11. PECL Switching Characteristics
PARAMETERS
SYMBOL
FREQ.
CONDITIONS MIN. TYP. MAX. UNITS
Clock Rise & Fall Times
Clock Rise & Fall Times
<150MHz
0.2
0.5
0.7
tr & tf
@20/80% - PECL
>150MHz
<320MHz
@80/20% - PECL
0.2
0.4
0.55
ns
PECL Levels Test Circuit
OUT
VDD
50Ω
2.0V
PECL Output Skew
OUT
50%
50Ω
OUT
OUT
80%
50%
20%
OUT
t_R
OUT
t_SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
t_F
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 12/14/06 Page 7