PL580-35 Datasheet, PDF (6/10 Pages) PhaseLink Corporation – 38MHz-320MHz Low Phase Noise VCXO

(Preliminary) PL580-35/37/38/39
38MHz-320MHz Low Phase Noise VCXO
8. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
VDD Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
VOD
ΔVOD
VOH
VOL
VOS
ΔVOS
IOXD
IOSD
CONDITIONS
RL = 100 Ω
(see figure)
Vout = VDD or GND
VDD = 0V
9. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
RL = 100 Ω
CL = 10 pF
(see figure)
MIN.
247
-50
0.9
1.125
0
MIN.
0.2
0.2
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Levels Test Circuit
OUT
V_OD
OUT
50Ω
V_OS
50Ω
LVDS Switching Test Circuit
OUT
C_L = 10pF
V_DIFF
OUT
C_L = 10pF
R_L = 100Ω
LVDS Transistion Time Waveform
OUT
OUT
0V (Differential)
V_DIFF
0V
20%
80%
t_R
80%
20%
t_F
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 12/14/06 Page 6