PL680-37 Datasheet, PDF (5/10 Pages) PhaseLink Corporation – 38-640MHz Low Phase Noise XO

4. Jitter Specifications
PARAMETERS
CONDITIONS
Integrated jitter RMS
Integrated 12 kHz to 20 MHz
Period jitter RMS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
Period jitter Peak-to-
Peak
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
(Preliminary) PL680-37/38/39
38-640MHz Low Phase Noise XO
FREQUENCY
106.25MHz
156.25MHz
212.5MHz
312.5MHz
622.08MHz
106.25MHz
156.25MHz
212.5MHz
312.5MHz
622.08MHz
106.25MHz
156.25MHz
212.5MHz
312.5MHz
622.08MHz
MIN.
TYP.
0.4
0.4
0.4
0.4
0.4
3
3
3
3
6
20
20
20
20
40
MAX.
0.5
0.5
0.5
0.5
0.5
5
5
5
5
8
30
30
30
30
50
UNITS
ps
ps
ps
5. Phase Noise Specifications
PARAMETERS
Phase Noise
relative to carrier
(typical)
FREQ.
106.25MHz
156.25MHz
212.5MHz
312.5MHz
622.08MHz
@10Hz
-66
-62
-62
-59
-49
@100Hz
-96
-92
-92
-85
-84
@1kHz
-122
-120
-118
-117
-111
@10kHz
-132
-132
-126
-128
-120
@100kHz
-126
-128
-120
-125
-118
@1M
-144
-140
-140
-139
-128
@10M
-150
-150
-150
-148
-138
UNITS
dBc/Hz
6. CMOS Electrical Characteristics
PARAMETERS
Output drive current
Output Clock Rise/Fall Time
Output Clock Rise/Fall Time
SYMBOL
IOH
IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
0.3V ~ 3.0V with 15 pF load
20%-80% with 50Ω Load
MIN.
30
30
TYP. MAX.
0.7
0.3
UNITS
mA
mA
ns
ns
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 11/28/05 Page 5