PL611-30 Datasheet, PDF (5/7 Pages) PhaseLink Corporation – Programmable Quick Turn Clock

P Preliminary L611-30
Programmable Quick Turn Clock^TM
Figure 1 below describes how to terminate the differential CMOS outputs of PhaseLink’s PL611-30 Programmable QTC clock
for use with PECL or LVDS inputs.
The unique feature of differential CMOS outputs allows great flexibility for board designers. By standardizing on one termination
scheme you can use the PL611-30 for all your LVDS and PECL clock requirements up to 375MHz.
CMOS Output
R1
50Ω line
+3.3V
R2
Input
R3
Complementary
CMOS Output
R3
R1
50Ω line
3.3V
R2
Complementary
Input
PECL LVDS
2.35V 1.40V
0V
+3.3V
1.59V 1.10V
Component selection
For PECL input For LVDS input
R1 = 130Ω
R2 = 82Ω
R3 = 130Ω
R1 = 360Ω
R2 = 82Ω
R3 = 130Ω
Notes:
Place R1 as close to the CMOS outputs as
possible.
Place R2 and R3 as close to the PECL/LVDS
inputs as possible.
Figure 1
The above layout allows the PL611-30 to drive either a PECL or LVDS input by simply changing the value of R1.
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