PL580-37 Datasheet, PDF (5/10 Pages) PhaseLink Corporation – 38MHz-320MHz Low Phase Noise VCXO

(Preliminary) PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
4. General Electrical Specifications
PARAMETERS SYMBOL
CONDITIONS
Supply Current,
Dynamic (with
Loaded Outputs)
38MHz<Fout<100MHz
IDD
PECL/LVDS/CMOS
100MHz<Fout<320MHz
Operating Voltage
VDD
Output Clock
Duty Cycle
@ 50% VDD (CMOS)
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
Short Circuit
Current
Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load.
MIN.
2.97
45
45
45
5. Jitter Specifications
TYP.
50
50
50
±50
MAX.
65/45/30
80/60/40
3.63
55
55
55
UNITS
mA
V
%
mA
PARAMETERS
Integrated jitter RMS
Period jitter RMS
Period jitter Peak-to-
Peak
CONDITIONS
Integrated 12 kHz to 20 MHz
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
FREQUENCY
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
77.76MHz
155.52MHz
311.04MHz
MIN.
TYP.
0.4
0.4
2.5
3
4
18
20
25
MAX.
0.5
0.5
4
5
7
30
30
35
UNITS
ps
ps
ps
6. Phase Noise Specifications
PARAMETERS FREQ. @10Hz
Phase Noise
77.76MHz
-66
relative to
155.52MHz -62
carrier (typical)
311.04MHz -59
Note: Phase Noise measured at VCON = 0V.
@100Hz
-96
-92
-86
@1kHz
-124
-120
-116
@10kHz
-134
-132
-129
@100kHz
-132
-128
-124
@1M
-145
-144
-140
@10M
-149
-150
-148
UNITS
dBc/Hz
7. CMOS Electrical Characteristics
PARAMETERS
Output drive current
Output Clock Rise/Fall Time
Output Clock Rise/Fall Time
SYMBOL
IOH
IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V
VOL = 0.4V, VDD = 3.3V
0.3V ~ 3.0V with 15 pF load
20%-80% with 50Ω Load
MIN.
30
30
TYP. MAX.
0.7
0.3
UNITS
mA
mA
ns
ns
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/29/05 Page 5