PL580-37 Datasheet, PDF (1/10 Pages) PhaseLink Corporation – 38MHz-320MHz Low Phase Noise VCXO

(Preliminary) PL580-37/38/39
38MHz-320MHz Low Phase Noise VCXO
FEATURES
• Less than 0.4ps RMS (12KHz-20MHz) phase
jitter for all frequencies.
• Less than 25ps (typ.) peak to peak jitter for all
frequencies.
• Low phase noise output (@ 1MHz frequency
offset
∗ -144dBc/Hz for 155.52MHz
∗ -140dBC/Hz for 311.04MHz
• 19MHz-40MHz crystal input.
• 38MHz-320MHz output.
• Available in PECL, LVDS, or CMOS outputs.
• No external varicap required.
• Output Enable selector.
• Wide pull range (+/-200ppm).
• 3.3V operation.
• Available in 3x3 QFN or 16-pin TSSOP
packages.
DESCRIPTION
The PL580-3X is a monolithic low jitter and low
phase noise VCXO, capable of 0.4ps RMS phase
jitter and CMOS, LVDS, or PECL outputs, covering a
wide frequency output range up to 320MHz. It allows
the control of the output frequency with an input
voltage (VCON), using a low cost crystal.
The frequency selector pads of PL580-3X enable
output frequencies of (2, 4, 8, or 16) * F_XIN. The
PL580-3X is designed to address the demanding
requirements of high performance applications such
as SONET, GPS, Video, etc.
PACKAGE PIN ASSIGNMENT
VDDANA 1
XIN 2
XOUT 3
SEL2^ 4
OE_CTRL 5
VCON 6
GNDANA 7
LP 8
16 SEL0^
15 _SEL1^
14 _GNDBUF
13 _QBAR
12 _VDDBUF
11 _Q
10 GNDBUF
9 LM
16-pin TSSOP
XOUT
SEL2^
OE_CTRL
VCON
12 11 10 9
13
8
14
7
PL580-3X
15
6
16
5
1234
GNDBUF
QBAR
VDDBUF
Q
3x3 QFN
Note1: QBAR is used for single ended CMOS output.
Note2: ^ Denotes internal pull up resistor.
BLOCK DIAGRAM
VCON
XIN
XOUT
VARICAP
XTAL
OSC
VCO
Divider
Phase
Detector
Charge
Pump
L o+o p
Filter
VCO
(F_XiNx16)
Output
Divider
(1,2,4,8)
QBAR
Q
OE
Performance Tuner
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/29/05 Page 1