PLL620-38 Datasheet, PDF (3/6 Pages) PhaseLink Corporation – PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)

PLL620-38/-39
PECL and LVDS Low Phase Noise XO (for 32.5-130MHz Output)
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
CONDITIONS
IDD
PECL/LVDS
VDD
@ 1.25V (LVDS)
@ VDD – 1.3V (PECL)
MIN. TYP.
2.97
45
50
45
50
±50
MAX.
100/80
3.63
55
55
UNITS
mA
V
%
mA
4. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Integrated jitter RMS
CONDITIONS
77.76MHz
77.76MHz
Integrated 12kHz to 20MHz at 77.76MHz
MIN. TYP. MAX. UNITS
2.5
ps
18.5
ps
0.5
ps
5. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
77.76MHz
@10Hz
-75
@100Hz
-95
@1kHz
-125
@10kHz @100kHz
-145
-155
UNITS
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/15/05 Page 3