PLL620-38 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)

PLL620-38/39
PECL and LVDS Low Phase Noise XO (32.5 to 130MHz output)
FEATURES
• 65MHz to 130MHz Crystal input.
• Output range: 32.5MHz – 130MHz (no PLL).
• Low Injection Power for crystal, 50uW.
• PECL (PLL620-38) or LVDS output (PLL620-39).
• Supports 2.5V or 3.3V-Power Supply.
• Available in 16-Pin TSSOP.
DESCRIPTION
The PLL620-38/-39 is a family of XO IC’s specifically
designed to work with high frequency fundamental or
3^rd OT crystals from 65MHz to 130MHz, with
selectable PECL or LVDS outputs. They achieve
very low current into the crystal resulting in better
overall stability. Their very low jitter makes them
ideal for the most demanding timing requirements.
PIN CONFIGURATION
!
Note: ^ designates internal pull-up resistor.
BLOCK DIAGRAM
Oscillator
XIN ^Amplifier
XOUT
OE
Q
Q
S2
PLL620-38/-39
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL620-38
PLL620-39
OE
0
(Default)
1
0
1
(Default)
State
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by PECL levels for PLL620-38
Logical states defined by CMOS levels for PLL620-39
OUTPUT FREQUENCY SELECTOR
S2
Output
0
1(Default)*
Input/2
Input
*Internally set to ‘Default’ through 60K pull-up resistor
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 09/15/05 Page 1