PL611S-28 Datasheet, PDF (2/9 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock

P (Preliminary) L611s-28
1.8V-3.3V PicoPLL^TM, World’s Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK[0:1]
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
• Low: 4mA
• Std: 8mA (default)
• High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
• OE - input
• PDB - input
• FSEL – input
• HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
OE, PDB,
FSEL, CLK1
Pin Assignment
SOT SC70 DFN
Pin # Pin# Pin#
1
2
2
Type
I/O
Description
This programmable I/O pin can be configured as an Output Enable
(OE) input, Power Down (PDB) input, On-the-Fly Frequency Switching
Selector (FSEL)input or CLK1 clock output. This pin has an internal
60KΩ pull up resistor (OE, PDB & FSEL Only).
The OE and PDB features can be programmed to allow the output to
float (Hi Z), or to operate in the ‘Active low’ mode.
State
OE
PDB
FSEL
0
Disable CLK Power Down Mode Frequency ‘2’
1 (default) Normal mode Normal mode
Frequency ‘1’
GND
XIN, FIN
XOUT
VDD
CLK0
2
1
3
P GND connection
3
3
1
I Crystal or Reference input pin
Crystal Output pin
4
4
6
O
Do Not Connect (DNC ) when FIN is present
5
5
5
P VDD connection
6
6
4
O Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 3/9/07 Page 2