PL611S-28 Datasheet, PDF (1/9 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock

P (Preliminary) L611s-28
1.8V-3.3V PicoPLL^TM, World’s Smallest Programmable Clock
FEATURES
• Designed for Very Low-Power applications
• Offered in Tiny GREEN/RoHS compliant packages
o 6-pin DFN (2.0mmx1.3mmx0.6mm)
o 6-pin SC70 (2.3mmx2.25mmx1.0mm)
o 6-pin SOT23 (3.0mmx3.0mmx1.35mm)
• Input Frequency:
o Fundamental Crystal: 10MHz to 50MHz
o Reference Input: 1MHz to 200MHz
• Accepts >0.1V reference signal input voltage
• Output Frequency:
o <65MHz @ 1.8V operation
o <90MHz @ 2.5V operation
o <125MHz @ 3.3V operation
• Disabled outputs programmable as HiZ or Active Low.
• Low current consumption:
o <1.2mA @ 27MHz
o < 5µA when PDB is activated
• Single 1.8V, 2.5V, or 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
DESCRIPTION
The PL611s-28 consumes very low-power while
producing high performance clock outputs of up to
55MHz. Designed for low-power applications with
very stringent space requirement, PL611s-28
consumes about 1.2mA, while producing 2 distinct
outputs of 27MHz and 13.5MHz. Designed to fit in a
small SOT, SC70, or SOT23 package for high
performance applications, the PL611s-28 offers
excellent phase noise and jitter performance. The
power down feature of PL611s-28, when activated,
allows the IC to consume less than 5µA of power,
while its programming flexibility allows generating
any output, using a low-cost crystal or reference
input. In addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(FOUT, FREF, FREF/2) output.
PACKAGE PIN CONFIGURATION
XIN/FIN ₁
OE, PDB, FSEL, CLK1 2
GND ₃
6 ^XOUT
5 ^VDD
4 ^CLK0
DFN-6L
(2.0mmx1.3mmx0.6mm)
GND ₁
OE, PDB,
FSEL, CLK1 ²
6 ^CLK0
5 ^VDD
XIN/FIN _{3 4} XOUT
SC70-6L
(2.3mmx2.25mmx1.0mm)
OE, PDB,
FSEL, CLK1 ¹
GND 2
XIN/FIN ₃
6 CLK0
5 ^VDD
4 XOUT
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL _Fref ^R-counter
OSC
(8-Bit)
Programmable
CLoad
M-counter
(11-Bit)
Phase
Detector
Fvco=Fref* (2 * M /R)
Charge
Pump
Loop
Filter
VCO
P-counter
Fout=Fvco / (2 *P) ^(5-Bit)
CLK0
Programmable Function
Programming
Logic
OE, FSEL,
PDB, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 3/9/07 Page 1