PL611S-26 Datasheet, PDF (2/8 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM Programmable Clock

P (Preliminary) L611s-26
1.8V-3.3V PicoPLL^TM Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
• Low: 4mA
• Std: 8mA (default)
• High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
• OE - input
• PDB - input
• CLK1 – output
PACKAGE PIN CONFIGURATION AND DESCRIPTION
FIN 1
OE,PDB,CLK1 2
GND ₃
6 FSEL
5 ^VDD
4 ^CLK0
OE, PDB, CLK1 1
GND 2
FIN ₃
6 CLK0
5 ^VDD
4 ^FSEL
DFN-6L
(2.0mmx1.3mmx0.6mm)
SOT23-6L
(3.0mmx3.0mmx1.35mm)
PIN DESCRIPTION
Name
OE,
PDB,
CLK1
Pin Assignment
DFN Pin# SOT Pin #
2
1
Type
I/O
Description
This programmable I/O pin can be configured as an Output Enable (OE)
input, Power Down input (PDB) or CLK1 Clock output. This pin has an
internal 60KΩ pull up resistor (OE and PDB functions only).
Pin State
OE
PDB
0
1 (default)
Disable CLK
Normal mode
Power Down Mode
Normal mode
GND
3
FIN
1
FSEL
6
VDD
5
CLK0
4
2
P GND connection
3
I Reference input pin
Frequency Switching Input pin. This pin has an internal 60KΩ pull up
resistor.
4
I
FSEL
0
State
Frequency 2
1 (default)
Frequency 1
5
P VDD connection
6
O Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 12/12/06 Page 2