PL611S-18 Datasheet, PDF (2/9 Pages) PhaseLink Corporation – 0.5kHz-125MHz MHz to KHz Programmable ClockTM

P (Preliminary) L611s-18
0.5kHz-125MHz MHz to KHz Programmable Clock^TM
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M=8 bit
R= 5 bit
P= 14 bit
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
• Low: 4mA
• Std: 8mA (default)
• High: 16mA
Programmable
Input/Output
One output pin can be configured as:
• OE - input
• FSEL - input
• PDB – input
• CLK1 – output
• Programmable CLoad
PACKAGE PIN CONFIGURATION AND ASSIGNMENT
XIN/FIN 1
GND 2
CLK0 3
CLK0 1
6 XOUT
GND 2
5 OE,PDB,FSEL,CLK1
4 VDD
XIN/FIN 3
6 VDD
5
OE, PDB,
FSEL, CLK1
4 XOUT
DFN-6L
(2.0mmx1.3mmx0.6mm)
SC70-6L
(2.3mmx2.25mmx1.0mm)
CLK0 1
GND 2
XIN/FIN 3
6 VDD
5
OE, PDB,
FSEL, CLK1
4 XOUT
SOT23-6L
(3.0mmx3.0mmx1.35mm)
Name
XIN, FIN
GND
CLK0
VDD
Pin Assignment
DFN SC70 SOT
Pin # Pin# Pin#
1
3
3
2
2
2
3
1
1
4
6
6
OE, PDB,
FSEL, CLK1
5
5
5
Type
Description
I Crystal or Reference input pin.
P GND connection
O Programmable Clock Output
P VDD connection
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB), Frequency Select
input (FSEL) or CLK1 output. This pin has an internal 60KΩ
pull up resistor on OE, PDB and FSEL.
I/O
State
OE
PDB
FSEL
0
Tri-state CLK Power Down Mode
1 (default) Operating mode Operating mode
Bank 0
Bank 1
XOUT
6
4
4
O Crystal Output pin. Do Not Connect if FIN is used.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 2/23/07 Page 2