PL611S-02 Datasheet, PDF (2/8 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock

P (Preliminary) L611s-02
1.8V-3.3V PicoPLL^TM, World’s Smallest Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * M / (R * P)
Where M = 11 bit
R = 8 bit
P = 5 bit
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
• Low: 4mA
• Std: 8mA (default)
• High: 16mA
Programmable
Input/Output
One output pin can be configured
as:
• OE - input
• PDB - input
• FSEL - input
• CLK1 – output
PACKAGE PIN ASSIGNMENT
Name
Pin Assignment
SOT23 SC70 DFN
Pin # Pin# Pin#
Type
Description
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB), On-the-Fly
Frequency Switching Selector (FSEL), or CLK1 clock output
This pin has an internal 60KΩ pull up resistor for OE, PDB &
OE, PDB,
FSEL, CLK1
1
2
2
I/O ^FSEL.
State
OE
PDB
FSEL
0
Tri-State CLK Power Down Mode Frequency ‘2’
1 (default) Normal mode Normal mode Frequency ‘1’
GND
XIN, FIN
XOUT
VDD
CLK0
2
1
3
P GND connection
3
3
1
I Crystal or Reference Clock input pin
Crystal Output pin
4
4
6
O
Do Not Connect (DNC ) when FIN is present
5
5
5
P VDD connection
6
6
4
O Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 12/12/06 Page 2