PL611S-02 Datasheet, PDF (1/8 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM, World’s Smallest Programmable Clock

P (Preliminary) L611s-02
1.8V-3.3V PicoPLL^TM, World’s Smallest Programmable Clock
FEATURES
• Lowest-power, smallest Programmable PLL
• Very low Jitter and Phase Noise
• Output Frequency up to:
o 133MHz @ 1.8V operation
o 166MHz @ 2.5V operation
o 200MHz @ 3.3V operation
• Input Frequency:
o Fundamental Crystal: 10MHz to 50MHz
o Reference Clock: 1MHz to 200MHz
• Accepts >0.1V reference signal input voltage
• One I/O pin can be configured as Output Enable (OE),
Frequency switching (FSEL), Power Down (PDB)
input, or CLK1 output.
• <10µA current consumption with PDB active.
• Single 1.8V, 2.5V, or 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
• Available in 6-pin DFN, SOT23, and SC70
GREEN/RoHS compliant packages.
DESCRIPTION
The PL611s-02 is a low-power, small form factor,
high performance OTP-base programmable
frequency synthesizer and a member of PhaseLink’s
PicoPLL Factory Programmable ‘Quick Turn Clocks.
Designed to fit in a small DFN, SC70, or SOT23
package for a broad range of applications, the
PL611s-02 offers the best phase noise and jitter
performance, and power consumption of its rivals. .
In addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(FOUT, FREF, FREF/2) output. The power down
feature of PL611s-02, when activated, allows the IC
to consume less than 10µA of power, while its
programming flexibility allows generating any output,
up to 200MHz using a low-cost crystal or reference
input.
PACKAGE PIN CONFIGURATION
XIN/FIN ¹
OE, PDB, FSEL, CLK1 2
GND 3
6 XOUT
5 VDD
4 CLK0
GND 1
OE, PDB,
FSEL, CLK1
2
XIN/FIN 3
6 _CLK0
5 VDD
4 XOUT
DFN-6L
(2.0mmx1.3mmx0.6mm)
BLOCK DIAGRAM
SC70-6L
(2.3mmx2.25mmx1.0mm)
OE, PDB,
FSEL, CLK1 ¹
GND 2
XIN/FIN ₃
6 CLK0
5 ^VDD
4 ^XOUT
SOT23-6L
(3.0mmx3.0mmx1.35mm)
XIN/FIN
XOUT
XTAL
OSC
Programmable
CLoad
F_REF
R-Counter
(8-bit)
M-Counter
(11-bit)
Phase
Detector
F_VCO = F_REF * (2 * M/R)
Charge
Pump
Loop
Filter
VCO
Programmable Function
P-Counter
F_OUT = F_VCO / ( 2 * P) ^(5-bit)
Programming
Logic
CLK0
OE, PDB,
FSEL, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 12/12/06 Page 1