PL610-01 Datasheet, PDF (2/11 Pages) PhaseLink Corporation – 1.8V to 3.3V, 1MHz to 130MHz XO IC

P (Preliminary) L610-01
1.8V to 3.3V, 1MHz to 130MHz XO IC
KEY PROGRAMMING PARAMETERS (Optional)
CLK[0:1]
Output Frequency
FOUT = FREF / P*
(*: P is an Odd/Even Divider)
Where P = 6 bit
CLK0 = FREF, FREF/2 or FREF / P
CLK1 = FREF, FREF/2 or CLK0
Output Drive Strength
Programmable
Input/Output
Three optional drive strengths
to choose from:
 Low: 4mA
 Std: 8mA (default)
 High: 16mA
One output pin can be configured
as:
 OE - input
 PDB - input
 CLK1 – output
PACKAGE PIN AND DIE PAD ASSIGNMENT
Name
Pin Assignment
Type
DFN-6L SOT23-6L
Description
XIN, FIN
1
3
I Crystal or Reference Clock input pin
OE, PDB,
2
CLK1
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB) input or CLK1
clock output. This pin has an internal 60KΩ pull up resistor
for OE and 10MΩ pull up resistor for PDB.
1
I/O
State
OE
PDB
0
Tri-state CLK Power Down Mode
1 (default) Normal mode
Normal mode
GND
CLK0
VDD
XOUT
3
2
P GND connection
4
6
O Programmable Clock Output
5
5
P VDD connection
Crystal Output pin
6
4
O
Do Not Connect (DNC ) when FIN is present
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 4/2/07 Page 2