PL611S-06 Datasheet, PDF (1/8 Pages) PhaseLink Corporation – Low-Power Programmable Quick Turn ClockTM

P (Preliminary) L611s-06
Low-Power Programmable Quick Turn Clock^TM
FEATURES
• Advanced low-power, space saving programmable
PLL design
• Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
• Up to 2 programmable clock outputs
• CMOS output frequency up to 35MHz.
• Accepts Crystal or Ref Clock input
o Fundamental Crystal: 10MHz to 30MHz
o Reference Input: 1MHz to 100MHz
• Accepts >0.1V reference signal input voltage
• Single 1.8V, 2.5V, or 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
• Available in 6-pin DFN, SC70, and SOT23, GREEN /RoHS
compliant packages
DESCRIPTION
The PL611s-06 is a low-power general purpose
frequency synthesizer and a member of PhaseLink’s
Programmable ‘Quick Turn Clock (QTC)’ family.
PhaseLink’s PL611s-06 can generate two system
clock frequencies of up to 35MHz from a 10MHz to
30MHz fundamental crystal or a 1MHz to 100MHz
Reference clock source. The PL611s-06 offers the
best phase noise and jitter performance, and power
consumption of its rivals. Cascading of the ICs to
produce additional clock frequencies is also
supported.
PACKAGE PIN CONFIGURATION
XIN, FIN 1
OE, CLK1 ₂
GND ₃
GND _{1 6} CLK0
6
5
XOUT
VDD
OE, CLK1
2
5 ^VDD
4 ^CLK0 _{XIN, FIN}
3
4
XOUT
DFN-6L
(2.0mmx1.3mmx0.6mm)
SC70-6L
(2.3mmx2.25mmx1.0mm)
OE, CLK1 1 6 CLK0
GND 2 5 VDD
XIN, FIN 3 4 XOUT
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
OSC
Programmable
CLoad
F_REF
R-Counter
(8-bit)
M-Counter
(11-bit)
Phase
Detector
F_VCO = F_REF * (2 * M/R)
Charge
Pump
Loop
Filter
VCO
Programmable Function
P-Counter
F_OUT = F_VCO / ( 2 * P) ^(5-bit)
Programming
Logic
CLK
OE, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 12/12/06 Page 1