PL611-07 Datasheet, PDF (1/4 Pages) PhaseLink Corporation – Programmable Quick Turn Clock

PL611-07
Programmable Quick Turn Clock^TM
FEATURES
• Advanced programmable PLL design
• Very low Jitter and Phase Noise (30-70ps Pk-Pk typical)
• Up to 2 programmable outputs
• Output frequency up to 75MHz CMOS
• Programmable Output Enable (OE) pin
• Accepts Crystal clock input
o Fundamental crystal: 10MHz-30MHz
o Reference input: Up to 100MHz
• Single 2.5V or 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
• Available in 6-pin SOT Green/RoHS compliant Pkg.
PIN CONFIGURATION
CLK1 1
GND 2
XIN/FIN 3
6 VDD
5 CLK2, OE
4 XOUT
SOT- 23
DESCRIPTION
The PL611-07 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
Programmable ‘Quick Turn Clock (QTC)’ family.
PhaseLink’s PL611-07 offers generating two system
clock frequencies of up to 75MHz form a 10-30MHz
fundamental crystal or a Reference clock source.
One clock output can be programmed to operate as
OE or be used as a Reference output. Cascading of
the ICs to produce additional clock frequencies is
also supported.
BLOCK DIAGRAM
PIN DESCRIPTION
Name
CLK1
Pin
#
Type
Description
1
O Programmable Clock Output
GND
2
XIN/FIN 3
XOUT
4
P GND connection
I
Crystal or Reference input
pin
O Crystal output pin
CLK2,
OE
5
VDD
6
Programmable Clock or
B _{Reference Output, or OE}
P
VDD connection
(2.25~3.63V)
XIN/FIN
XOUT
Xtal ^FRef R-counter
OSC
(8-bit)
M - counter
(10-bit)
Phase
Detector
Charge
Pump
Loop
Filter
F_VCO = F _Ref. * (2 * M /R)
VCO
P - counter
(5-bit)
F_out = F_VCO / (2 * P)
Programmable Function
Selectable
/1,/2,/4,/8
Selectable
/1,/2
CLK[1:2]
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 08/17/05 Page 1