PAS5101PE Datasheet, PDF (13/20 Pages) Pixart Imaging Inc. – CMOS 1.3MEGA DIGITAL IMAGE SESNSOR

PAS5101PE Specification
During read cycle, the master generates start condition and then place the 1^st byte data that are combined
slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits
DATA was also placed on SDA line by PAS5101PE. The 8 bits data was read from PAS5101PE internal
control register that address was assigned by previous write cycle. Follow the master acknowledgment,
the PAS5101PE place the next 8 bits data ( address is increment automatically ) on SDA line and then
transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte
read, Am is no longer generated by master but instead by keep SDA line high. The slave ( PAS5101PE )
must releases SDA line to master to generate STOP condition.
4.3. I2C^TM Bus Timing
4.4. I2C^TM Bus Timing Specification
Parameter
SCL clock frequency.
Hold time ( repeated ) Start condition.
After this period, the first clock pulse is generated.
Low period of the SCL clock.
High period of the SCL clock.
Set-up time for a repeated START condition.
Symbol
f_scl
t_HD:STA
t_LOW
t_HIGH
t_SU;STA
Standard Mode
Min. Max
10
400
4.0
-
4.7
-
0.75
-
4.7
-
Unit
KHz
μs
μs
μs
μs
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PixArt Imaging Inc.
E-mail: [e-mail]
v1.0 2005/4/27