TDA8779 Datasheet, PDF (9/20 Pages) NXP Semiconductors – 10-bit converter interface ADC/DAC for quadrature transceiver

Philips Semiconductors
10-bit converter interface (ADC/DAC) for
quadrature transceiver
Objective specification
TDA8779
SYMBOL
PARAMETER
STANDBY MODE OUTPUT DELAY TIMES; STDBYA
t_d(stb)LH
t_d(stb)HL
standby (LOW-to-HIGH transition)
start-up (HIGH-to-LOW transition)
CROSSTALK ON THE ADC
α_ct
crosstalk into the ADC
DAC PART
DIGITAL INPUTS: D0D TO D9D AND CLKD
V_IL
LOW level input voltage
V_IH
HIGH level input voltage
I_IL
LOW level input current
I_IH
HIGH level input current
DIGITAL INPUT; STDBYD
V_IL
LOW level input voltage
V_IH
HIGH level input voltage
I_IL
LOW level input current
I_IH
HIGH level input current
TIMING: see Fig.5
f_CLK(max)
t_CH
t_CL
t_r
t_f
t_s
t_h
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
clock rise time
clock fall time
input data set-up time
input data hold time
ANALOG OUTPUTS; note 1
V_o(p-p)
Z_oL
output voltage (peak-to-peak value)
output load impedance
TRANSFER FUNCTION
INLD
integral non linearity
DNLD
differential non linearity
B
maximum bandwidth
CONDITIONS
MIN. TYP. MAX. UNIT
−
−
100 µs
−
−
100 µs
f_CLK(DAC) = 16.384 MHz;
−
f_CLK(ADC) = 8.192 MHz;
T_amb = 25°C; both DACs
switching between input
codes 0 and 1023; one
ADC 1 V (p-p) sine wave at
4 MHz and the other ADC
set at the middle code
−
−55 dB
0
2.2
−200
−10
0
2.2
−1
−
20
20
20
−
−
10
0
full-scale
tbf
see Fig.6
−
−
ramp input; f_CLK = 20 MHz −
ramp input; f_CLK = 20 MHz; −
full scale; T_amb = 25°C
5.5
−
−
−120
−
0.6 V
V_CCD2 V
0
µA
+10 µA
−
0.6 V
−
V_CCD2 V
0
+1 µA
−
1
µA
−
−
−
−
−
−
4
−
4
−
tbf −
tbf −
MHz
ns
ns
ns
ns
ns
ns
1
tbf V
15 −
pF
0.3 −
kΩ
±3 −
±0.75 −
−
−
LSB
LSB
MHz
1996 Sep 18
9