TDA8779 Datasheet, PDF (8/20 Pages) NXP Semiconductors – 10-bit converter interface ADC/DAC for quadrature transceiver

Philips Semiconductors
10-bit converter interface (ADC/DAC) for
quadrature transceiver
Objective specification
TDA8779
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
ANALOG SIGNAL PROCESSING
Linearity
INLA
DNLA
integral non linearity
differential non linearity
ramp input; f_CLK = 20 MHz −
full-scale; ramp input;
−
f_CLK = 20 MHz
50% full-scale; ramp input; −
f_CLK = 20 MHz
±2 −
±0.5 −
±0.3 −
Noise floor; note 2
NF
noise floor
f_in = 5.1 MHz; 20 Msps
−
−60 −
Harmonics; note 3
THD
total harmonic distortion
f_i = 5.1 MHz; 20 Msps
−
−54 −
Spurious free dynamic range
SFDR
spurious free dynamic range
f_i = 5.1 MHz; 20 Msps
45
56 −
Matching between the I and Q channels
∆V
amplitude matching
∆ϕ
phase matching
f_in = 5.1 MHz;
f_CLK = 20 MHz;
T_amb = 25°C
f_in = 5.1 MHz;
f_CLK = 20 MHz;
T_amb = 25°C
−
−
6
−
−
2
Bandwidth
B
bandwidth maximum attenuation of
full-scale sine wave;
5.5
−
−
−0.3 dB
T_amb = 25°C;
50% full-scale sine wave; tbf
−
−
T_amb = 25°C;
TIMING: (THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME t_d); C_L = 15 pF; see Fig.3
t_ds
sampling delay time
t_h
output hold time
t_d
output delay time
V_CCO = 4.75 V
V_CCO = 3.15 V
V_CCO = 2.7 V
−
−
5
5
−
−
−
12 15
−
17 20
−
21 24
3-STATE OUTPUT DELAY TIMES; see Fig.4
t_dZH
output delay enable HIGH
t_dZL
output delay enable LOW
t_dHZ
output delay disable HIGH
t_dLZ
output delay disable LOW
−
14 18
−
16 20
−
16 20
−
14 18
LSB
LSB
LSB
dB
dB
dB
%
Deg
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
1996 Sep 18
8