TDA8767 Datasheet, PDF (9/20 Pages) NXP Semiconductors – 12-bit high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
12-bit high-speed Analog-to-Digital
Converter (ADC)
Preliminary specification
TDA8767
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
SIGNAL-TO-NOISE RATIO
S/N
signal-to-noise ratio
without harmonics;
−
f_clk = 30 MHz; f_i = 4.43 MHz
61
−
dB
Timing (C_L = 15 pF); note 4; see Fig.3
t_ds
sampling delay time
t_h
output hold time
t_d
output delay time
V_CCO = 4.75 V
V_CCO = 3.15 V
−
−
2
ns
8
−
−
ns
−
12
15
ns
15
18
ns
3-state output delay times; see Fig.4
t_dZH
enable HIGH
t_dZL
enable LOW
t_dHZ
disable HIGH
t_dLZ
disable LOW
−
14
18
ns
−
16
20
ns
−
16
20
ns
−
14
18
ns
Notes to the characteristics
1. The −3 dB (or −1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output,
the input being a full-scale sine wave.
2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
THD = 20 log-------------------------------------------------------F--------------------------------------------------------
(2nd)2 + (3rd)2 + (4th)2 + (5th)2 + (6th)2
F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data (see Fig.5).
4. Output data acquisition: the output data is available after the maximum delay of t_d.
1999 Feb 16
9