TDA8767 Datasheet, PDF (8/20 Pages) NXP Semiconductors – 12-bit high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
12-bit high-speed Analog-to-Digital
Converter (ADC)
Preliminary specification
TDA8767
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Voltage controlled regulator input V_ref (referenced to V_CCA)
V_ref(FS)
full scale fixed voltage
V_CCA = 5 V
−
V_i(p-p) − V_i(p-p) input voltage amplitude
differential mode
−
(peak-to-peak value)
single mode; V_i = 2.5 V
−
I_ref
input current at V_ref
−
Outputs (referenced to DGND)
3.175 −
V
2.0
−
V
2.0
−
V
10
−
µA
DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO DGND)
V_OL
LOW-level output voltage I_OL = 2 mA
V_OH
HIGH-level output voltage I_OH = −0.4 mA
I_O
output current in 3-state
0.5 V < V_O < V_CCO
Switching characteristics
0
−
V_CCO − 0.5 −
−20
−
0.5
V
V_CCD V
+20 µA
CLOCK FREQUENCY f_clk (see Fig.3)
f_clk(min)
minimum clock frequency
SH = HIGH
SH = LOW
−
−
1
−
−
1
f_clk(max)
maximum clock frequency
TDA8767H/1
10
−
−
TDA8767H/2
20
−
−
TDA8767H/3
30
−
−
t_CPH
clock pulse width HIGH
t_CPL
clock pulse width LOW
8.5
−
−
8.5
−
−
Analog signal processing; 50% clock duty factor; V_i − V_i = 2.0 V; V_ref = V_CCA − 2 V; see Table 1
MHz
kHz
MHz
MHz
MHz
ns
ns
LINEARITY
ILE
integral non-linearity
f_clk = 4 MHz; ramp input
−
DLE
differential non-linearity
f_clk = 4 MHz; ramp input;
−
no missing codes
OFER
offset error
V_CCA = V_CCD = V_CCO = 5 V; tbf
T_amb = 25 °C; V_i = V_i; output
code = 2047
GER
gain error amplitude; spread V_CCA = V_CCD = V_CCO = 5 V; tbf
from device to device
T_amb = 25 °C; V_i − V_i = 2.0 V
BANDWIDTH (f_clk = 30 MHz); note 1
B
analog bandwidth
−1 dB
−
−3 dB
−
t_STLH
analog input settling time full scale square wave;
−
LOW-to-HIGH transition
note 3
t_STHL
analog input settling time full scale square wave;
−
HICH-to-LOW transition
note 3
HARMONICS
THD
total harmonic distortion
f_clk = 30 MHz; f_i = 4.43 MHz; −
note 2
±3.0 ±4.0 LSB
±0.6 ±1
LSB
−
tbf
LSB
−
tbf
LSB
9
−
18
−
tbf
−
tbf
−
MHz
MHz
ns
ns
−64 −
dB
1999 Feb 16
8