TDA8315T Datasheet, PDF (9/16 Pages) NXP Semiconductors – Integrated NTSC decoder and sync processor

Philips Semiconductors
Integrated NTSC decoder
and sync processor
Preliminary specification
TDA8315T
SYMBOL
PARAMETER
CONDITIONS MIN.
HORIZONTAL PLL; NOTE 12 (FILTER CONNECTED TO PIN 4)
f_HR
holding range PLL
f_CR
catching range PLL
S/N
signal-to-noise ratio of the video input
signal at which the time constant is
switched
HYS
hysteresis at the switching point
note 2
−
±0.6
−
−
HORIZONTAL OUTPUT (PIN 2)
V_OH
HIGH level output voltage
I_O = 2 mA
2.4
V_OL
LOW level output voltage
I_O = 2 mA
−
I_O(sink)
output sink current
−
I_O(source)
output source current
−
t_W
pulse width
note 13
−
t_d
delay time between positive edge of the
−
horizontal output pulse and start of the
horizontal sync pulse at the input
BACK PORCH CLAMPING OUTPUT (PIN 10)
V_OH
HIGH level output voltage
I_O = 2 mA
2.4
V_OL
LOW level output voltage
I_O = 2 mA
−
I_O(sink)
output sink current
−
I_O(source)
output source current
−
t_W
pulse width
3.2
t_d
delay time between start of clamping pulse
5.2
and start of the start sync pulse
VERTICAL OUTPUT (PIN 7); NOTE 14
f_fr
free-running frequency
f_lock
locking range
divider value not locked
locking range (lines/frame)
V_OH
V_OL
I_O(sink)
I_O(source)
t_W
t_d
HIGH level output voltage
LOW level output voltage
output sink current
I_O = 2 mA
I_O = 2 mA
output source current
pulse width (6 line periods)
delay time between start of the vertical sync
pulse at the input and the positive edge of
the output pulse
−
54.6
−
488
2.4
−
−
−
−
−
TYP.
±0.9
±0.9
20
3
4.0
0.3
−
−
5.4
0
4.0
0.3
−
−
3.4
5.4
60
−
525
−
4.0
0.3
−
−
380
37.5
MAX. UNIT
±1.2
kHz
−
kHz
−
dB
−
dB
−
V
0.6
V
2
mA
2
mA
−
µs
−
µs
−
V
0.6
V
2
mA
2
mA
3.6
µs
5.6
µs
−
Hz
64.5
Hz
−
576
−
V
0.6
V
2
mA
2
mA
−
µs
−
µs
September 1994
9