SAA7151B Datasheet, PDF (9/49 Pages) NXP Semiconductors – Digital multistandard colour decoder with SCART interface DMSD2-SCART

Philips Semiconductors
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
Product specification
SAA7151B
Luminance processing
The luminance input signal, a digital CVBS format or an
8-bit luminance format (S-Video), is fed through a sample
rate converter to reduce the data rate to 13.5 MHz (Fig.5).
Sample rate is converted by means of a switchable
pre-filter. High frequency components are emphasized to
compensate for loss in the following chrominance trap
filter. This chrominance trap filter (f_o = 4.43 MHz or
f_o = 3.58 MHz centre frequency selectable) eliminates the
most of the colour carrier signal, therefore, it must be
bypassed for S-Video signals.
The high frequency components of the luminance signal
can be “peaked” in two bandpass filters with selectable
transfer characteristic. A coring circuit (±1 LSB) can
improve the signal, this signal is then added to the original
signal. A switchable amplifier achieves a common DC
amplification, because the DC gains are different in both
chrominance trap modes. Additionally, a cut-off sync pulse
is generated for the original signal in both modes.
Synchronization
The luminance output signal is fed to the synchronization
stage. Its bandwidth is reduced to 1 MHz in a low-pass
filter (sync pre-filter). The sync pulses are sliced and fed to
the phase detectors to be compared with the sub-divided
clock frequency. The resulting output signal is applied to
the loop filter to accumulate all phase deviations. There
are three groups of output timing signals:
a. signals related to data output signals (HREF)
b. signals related to the input signals (HSY, and HCL)
c. signals related to the internal sync phase
All horizontal timings are derived from the main counter,
which represents the internal sync phase. The HREF
signal only with its critical timing is phase-compensated in
relationship to the data output signal. Future circuit
improvements could slightly influence the processing
delays of some internal stages to achieve a changed
timing due to the timing groups b and c.
The HREF signal only controls the data multiplexer phase
and the data output signals.
All timings of the following diagrams are measured with
nominal input signals, for example coming from a pattern
generator. Processing delay times are taken between
input and data output, respectively between internal sync
reference (main counter = 0) and the rising edge of HREF.
Line locked clock frequency
LFCO is required in an external PLL (SAA7157) to
generate the line-locked clock frequency LL27 and CREF.
YUV-bus, digital outputs
The 16-bit YUV-bus transfers digital data from the output
interfaces to a feature box, or to the digital-to-analog
converter (DAC). Outputs are controlled via the I²C-bus in
normal selections, or they are controlled by output enable
chain (FEIN, pin 64). The YUV-bus data rate 13.5 MHz.
Timing is achieved by marking each second positive rising
edge of the clock LL27 synchronized by CREF.
YUV-bus formats
4 : 2 : 2 and 4 : 1 : 1
The output signals Y7 to Y0 are the bits of the digital
luminance signal. The output signals UV7 to UV0 are the
bits of the digital colour-difference signal. The frames in
the Tables 2 and 3 are the time to transfer a full set of
samples. In case of 4 : 2 : 2 format two luminance samples
are transmitted in comparison to one U and one V sample
within one frame. The time frames are controlled by the
HREF signal, which determines the correct UV data
phase. The YUV data outputs can be enabled or set to
3-state position by means of the FEIN signal. FEIN = LOW
enables the output; HIGH on this pin forces the Y and U/V
outputs to a high-impedance state (Fig.6).
April 1993
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