SA630_15 Datasheet, PDF (9/20 Pages) NXP Semiconductors – Single-Pole Double-Throw (SPDT) switch

NXP Semiconductors
SA630
Single-Pole Double-Throw (SPDT) switch
14. Application information
The typical application schematic and printed-circuit board layout of the SA630 evaluation
board is shown in Figure 19. The layout of the board is simple, but a few cautions must be
observed. The input and output traces should be 50 . If a symmetric isolation between
the two channels is desired, then the placement of the AC bypass capacitor is extremely
critical. The trace from AC_GND (pin 7) should be drawn back towards the package and
then be routed downwards. The capacitor should be placed straight down as close to the
device as practical.
For better isolation between the two channels at higher frequencies, it is also advisable to
run the two output/input traces at an angle. This arrangement also minimizes any
inductive coupling between the two traces. The power supply bypass capacitor should be
placed close to the device. Figure 5 shows the frequency response of the SA630. The
loss matching between the two channels is excellent to 1.2 GHz, as shown in Figure 7.
V_DD
+5 V
0.1 μF
INPUT
1
GND ₂
0.01 μF
3
ENCH1
4
a. Evaluation board schematic
SA630
0.01 μF
8
AC_GND
7
6 ^{GND 0.01 μF}
5
aaa-013989
0.01 μF
OUT1
OUT2
b. SA630 board layout
Fig 19. Evaluation board and layout
SA630
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 23 July 2014
aaa-013990
© NXP Semiconductors N.V. 2014. All rights reserved.
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