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SA630_15 Datasheet, PDF (5/20 Pages) NXP Semiconductors – Single-Pole Double-Throw (SPDT) switch
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NXP Semiconductors
SA630
Single-Pole Double-Throw (SPDT) switch
11. Static characteristics
Table 7. Static characteristics
VDD = +5 V; Tamb = 25 C; unless otherwise specified.
Symbol Parameter
Conditions
IDD
supply current
Vth
threshold voltage
VIH
HIGH-level input voltage
TTL/CMOS logic
logic 1 level;
enable channel 1
VIL
LOW-level input voltage
logic 0 level;
enable channel 2
IIL(ENCH1) LOW-level input current on pin ENCH1 ENCH1 = 0.4 V
IIH(ENCH1) HIGH-level input current on pin ENCH1 ENCH1 = 2.4 V
Min
40
[1] 1.1
2.0
0.3
1
1
[1] The ENCH1 input must be connected to a valid logic level for proper operation of the SA630.
Typ
170
1.25
-
-
0
0
Max
300
1.4
VDD
+0.8
+1
+1
Unit
A
V
V
V
A
A
12. Dynamic characteristics
Table 8. Dynamic characteristics
All measurements include the effects of the SA630 evaluation board (Figure 19). Measurement system impedance is 50 .
Symbol Parameter
Conditions
Min
Typ
Max
Unit
s21, s12 insertion loss (ON channel)
DC to 100 MHz
500 MHz
-
1
-
dB
-
1.4
-
dB
900 MHz
-
2
2.8
dB
s21, s12
isolation (OFF channel)[1]
10 MHz
100 MHz
70
80
-
dB
-
60
-
dB
500 MHz
-
50
-
dB
900 MHz
24
30
-
dB
s11, s22 return loss (ON channel)
DC to 400 MHz
900 MHz
-
20
-
dB
-
12
-
dB
s11, s22 return loss (OFF channel)
DC to 400 MHz
900 MHz
-
17
-
dB
-
13
-
dB
td(off)
turn-off delay time
50 % TTL to
(90 % to 10 %) RF
-
20
-
ns
tf(off)
tr(on)
Vtrt(p-p)
PL(1dB)
IP3
turn-off fall time
turn-on rise time
peak-to-peak transient voltage
output power at 1 dB gain compression
third-order intercept point
90 % to 10 % RF
10 % to 90 % RF
switching transients
DC to 1 GHz
100 MHz
-
5
-
ns
-
5
-
ns
-
165
-
mV
-
+18
-
dBm
-
+33
-
dBm
IP2
second-order intercept point
100 MHz
-
+52
-
dBm
NF
noise figure
Zo = 50 
100 MHz
-
1.0
-
dB
900 MHz
-
2.0
-
dB
[1] The placement of the AC bypass capacitor is critical to achieve these specifications. See Section 14 for more details.
SA630
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 23 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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