PCF5001 Datasheet, PDF (9/44 Pages) NXP Semiconductors – POCSAG Paging Decoder

Philips Semiconductors
POCSAG Paging Decoder
Product specification
PCF5001
handbook, halfpage
Vref ₁
28 FL
CN 2
27 DS
CP 3
VDD ₄
26 DO
25 OR
DI 5
24 BL
BS 6
23 AI
PD 7
PS 8
PCF5001T
22 ON
21 SR
X1 9
20 SK
X2 10
19 IE
TS 11
AH 12
OL 13
18 TT
17 ^VSS
16 OM
RE 14
15 AL
MCD455 - 1
handbook, halfpage
index
corner
IE 1
n.c. 2
SK 3
SR 4
ON 5
AI 6
n.c. 7
BL 8
PCF5001H
24 X2
23 X1
22 PS
21 n.c.
20 n.c.
19 PD
18 BS
17 DI
MLB048
Fig.3 Pin configuration PCF5001T (SOT136-1).
Fig.4 Pin configuration PCF5001H (SOT358-1).
7 FUNCTIONAL DESCRIPTION
The PCF5001 is a very low power Decoder and Pager
Controller specifically designed for use in new generation
radio pagers. The architecture of the PCF5001 allows for
flexible application in a wide variety of radio pager designs.
The PCF5001 is fully compatible with “CCIR radio paging
Code Number 1” (also known as the POCSAG code)
operating at the originally specified 512 bits/s data rate,
and also at the newly specified 1200 bits/s data rate
(2400 bits/s operation is also possible). The PCF5001 also
offers features which extend the basic flexibility and
efficiency of this code standard.
7.1 The PCF5001 supports two basic modes of
operation
In alert-only pager mode only a minimum number of
external components are required to build a complete
tone-only pager. Selection of operating states ON, OFF or
SILENT is achieved using a slider switch interface.
In display pager mode the state input logic is switched to
a bus interface structure. Received calls and messages
are transferred to an external microcontroller via the serial
microcontroller interface. A built-in voltage converter with
increased drive capabilities can supply doubled supply
voltage output, and appropriate logic level shifting on
microcontroller interface signals is provided.
Upon reception of valid calls one of eight different call
cadences is generated; upon status interrogation status
indication tones make the current status of the decoder
available to the user.
On-chip non-volatile 114-bit EEPROM storage is provided
to hold up to four user addresses, two frame numbers and
the programmed decoder configuration.
Synchronization to the input data stream is achieved using
the improved ACCESS^® algorithm, which allows for data
synchronization and re-synchronization without preamble
detection while minimizing battery power consumption by
receiver power control. One of four error correction
algorithms is applied to the received data to optimize the
call success rate.
1997 Mar 04
9