PCF5001 Datasheet, PDF (28/44 Pages) NXP Semiconductors – POCSAG Paging Decoder

Philips Semiconductors
POCSAG Paging Decoder
Product specification
PCF5001
SR
DO
ENA
B17
ENC
D17
DS
t _SDD
t _DSE
FR12
SPF
32
MCD472
Fig.20 EEPROM data transfer to microcontroller timing.
7.23 Test modes of the decoder
The decoder supports two test modes, which are intended
for use during pager production and type approval tests.
7.23.1 BOARD TEST MODE
‘Board test’ mode is selected by setting the PD input LOW
at any time. In this test mode the following features are
provided:
1. Receiver enable output is set constantly HIGH
2. Output AL is activated by a LOW-level on ON input
3. Output AH is activated by a HIGH-level on SR input
4. Outputs OL and OM are activated by a HIGH-level on
SK input.
Exit from ‘board test’ mode is achieved by setting input PD
HIGH.
7.23.2 PAGER TEST MODE (TYPE APPROVAL MODE)
‘Pager test’ mode is entered by reception of a valid call
while ‘board test’ mode is active, see above. In ‘pager test’
mode:
1. Call alert cadences are terminated after 2 seconds
2. Duplicate call suppression is disabled.
Exit from ‘pager test’ mode is achieved by disconnecting
the power supply from the decoder.
1997 Mar 04
28