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| BLM8G0710S-45AB_15 Datasheet, PDF (9/20 Pages) NXP Semiconductors – LDMOS 2-stage power MMIC | |||
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NXP Semiconductors
BLM8G0710S-45AB(G)
LDMOS 2-stage power MMIC
8.1 Possible circuit topologies
,Q$
G%ÄÂ
G%ÄÂ
,Q%
Fig 5. Dual section
2XW$
2XW%
DDD
6SOLWWHU
,Q
G%ÄÂ
È
G%Ä Â
&RPELQHU
È
2XW
Fig 6. Doherty
DDD
8.2 Ruggedness in class-AB operation
The BLM8G0710S-45AB and BLM8G0710S-45ABG are capable of withstanding a load
mismatch corresponding to VSWR = 10 : 1 through all phases under the following
conditions: f = <tbd> MHz; VDS = 32 V; IDq1 = <tbd> mA (carrier section, driver stage);
IDq2 = <tbd> mA (carrier section, final stage); IDq1 = <tbd> mA (peaking section, driver
stage); IDq2 = <tbd> mA (peaking section, final stage); Pi = <tbd> dBm (carrier section);
Pi = <tbd> dBm (peaking section). Pi is measured at CW and corresponding to PL(3dB)
under ZS = 50 ï load.
BLM8G0710S-45AB_S-45ABG
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 â 20 August 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 20
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