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| 74F50729 Datasheet, PDF (9/12 Pages) NXP Semiconductors – Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics | |||
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Philips Semiconductors
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
Product specification
74F50729
TEST CIRCUIT AND WAVEFORMS
VIN
PULSE
GENERATOR
VCC
VOUT
D.U.T.
NEGATIVE
PULSE
90%
tw
VM
10%
tTHL (tf )
VM
10%
tTLH (tr )
90%
AMP (V)
0V
RT
CL RL
Test Circuit for Totem-Pole Outputs
POSITIVE
PULSE
10%
tTLH (tr )
90%
VM
tw
tTHL (tf )
90%
VM
AMP (V)
10%
0V
DEFINITIONS:
RL = Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
Input Pulse Definition
family
74F
INPUT PULSE REQUIREMENTS
amplitude VM rep. rate
tw
tTLH
3.0V 1.5V 1MHz 500ns 2.5ns
tTHL
2.5ns
SF00006
1990 Sep 14
9
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