74F50729 Datasheet, PDF (5/12 Pages) NXP Semiconductors – Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics

Philips Semiconductors
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
Product specification
74F50729
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
10⁶ 10⁸
10¹⁰ 10¹²
10¹²
10¹¹
10,000 years
10¹⁰
MTBF in seconds
100 years ₁₀₉
10⁸
one year
10⁷
10¹⁴
10¹⁵ = f_Cf_I
10⁶
one week
7
8
9
10
t’ in nanoseconds
NOTE: V_CC = 5V, T_amb = 25°C, τ =135ps, To = 9.8 X 10⁶ sec
Figure 4.
SF00589
TYPICAL VALUES FOR τ AND T₀ AT VARIOUS V_CCS AND TEMPERATURES
T_amb = 0°C
T_amb = 25°C
V_CC
5.5V
τ
125ps
T₀
1.0 X 10⁹ sec
τ
138ps
T₀
5.4 X 10⁶ sec
5.0V
115ps
1.3 X 10¹⁰ sec
135ps
9.8 X 10⁶ sec
4.5V
115ps
3.4 X 10¹³ sec
132ps
5.1 X 10⁸ sec
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
SD RD CP D
Q
Q
MODE
↑↑XX
H
L Asynchronous set
↑↑XX
L
H Asynchronous reset
↑↑↑h
H
L Load ”1”
↑↑↑ l
L
H Load ”0”
↑ ↑ ↑ X NC
NC Hold
NOTES:
1. H = High–voltage level
2. h = High–voltage level one setup time prior to low–to–high clock
transition
3. L = Low–voltage level
4. l = Low–voltage level one setup time prior to low–to–high clock
transition
5. NC= No change from the previous setup
6. X = Don’t care
7. ↑ = Low–to–high clock transition
8. ↑ = Not low–to–high clock transition
LOGIC DIAGRAM
SD ^{4, 10}
RD ^{1, 13}
CP ^{3, 11}
2, 12
D
V_CC = Pin 14
GND = Pin 7
τ
160ps
167ps
175ps
T_amb = 70°C
T₀
1.7 X 10⁵ sec
3.9 X 10⁴ sec
7.3 X 10⁴ sec
5, 9
Q
6, 8
Q
SF00614
1990 Sep 14
5