P8XCX66 Datasheet, PDF (84/92 Pages) NXP Semiconductors – 80C51 8-bit CPU

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PIN
SDIP42 PLCC68
SYMBOL
TYPE INPUT LEVEL
OUTPUT TYPE
SLOPE OUTPUT IN OUTPUT ACTIVE STATE
CONTROL IDLE MODE AFTER RESET SW CONTROL
−
61
37
62
n.c.
P1.3
−
−
I/O TTL STr
−
open-drain
−
−
−
Yes
original state Z⁽²⁾
37
62
38
63
INT0
P1.4
I
TTL STr
I/O TTL STr
−
open-drain
−
−
−
Yes
original state Z⁽²⁾
38
63
39
64
39
64
40
65
40
65
41
66
T1
P1.5
SCL
P1.6
SDA
P1.7
I
TTL STr
I/O TTL STr
I/O TTL STr
I/O TTL STr
I/O TTL STr
I/O TTL STr
−
−
open-drain
Yes
open-drain
Yes
open-drain
Yes
open-drain
Yes
open-drain + Rpu⁽⁵⁾ Yes
−
−
original state Z⁽²⁾
HIGH⁽¹¹⁾
−
original state Z⁽²⁾
HIGH⁽¹¹⁾
−
original state Z⁽²⁾
41
−
V_SS
−
67
V_SS
42
68
V_DD
−
note 9
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Notes
1. A pull-up resistor must be present to prevent a floating input during normal/alternative mode when no external signal is applied to the pad.
Pull-up = present internally.
2. All ports are in input mode after reset; that means the value at the pin is determined by the external circuitry: pull-up registers Rext (and/or external
applied input).
3. A pull-up resistor must be present to prevent floating (digital) inputs if the pad is used for the analog inputs ADCO, ADCI and ADC2. This pull-up is
also present if these pins are used as port function. Pull-up is internally.
4. These pins are standard I/O cells SPF20PGD (2 mA PP slew-rate controlled).
5. A pull-up resistor must be present to prevent a floating input during nominal/alternative mode when no external signal is applied to the pad.
Pull-up = present internally.
6. Inverse of the Bp bit (located in OSCON).
7. After reset the Bp bit (located in OSCON) = 1, therefore output becomes LOW.
8. Its pull-down resistor is present internally (see Section 13.2).
9. For the SDIP42 package, pin P1.0 can be exchanged for a V_SS or V_DD, pin P1.7 for a V_SS.
10. For the PLCC68 package, pin P1.0 can be exchanged for a V_DD line.
11. Output is HIGH via external resistor.