P8XCX66 Datasheet, PDF (12/92 Pages) NXP Semiconductors – 80C51 8-bit CPU

Philips Semiconductors
Microcontrollers for PAL/SECAM TV
with OSD and VST
Product specification
P8xCx66 family
7 I/O FACILITY
7.1 I/O ports
The SDIP42 package has 28 I/O lines treated as
28 individual addressable bits or as 3 parallel 8-bit
addressable ports (Ports 0, 1 and 5) and one 4-bit port
(Port 3).
When these 28 I/O lines are used as input ports, the
corresponding bits in SFRs P0, P1, P3 and P5 should be
set to a logic 1 to facilitate the external input signal.
Ports 1, 3 and 5 also perform the following alternative
functions.
Port 1. Used for a number of special functions:
• Provides the external interrupt inputs (INT0 and INT1)
• Provides the 16-bit timer/counter inputs (T0 and T1)
• Provides the I²C-bus data and clock signals (SDA and
SCL)
• P1.0 and P1.7 can be used as external interrupt inputs.
Port 3. Only 4 lines available for alternative functions:
• 7-bit PWM output (PWM7)
• ADC inputs ADC0 to ADC2.
Port 5.
• Provides the 14-bit PWM output (TPWM)
• 7-bit PWMs outputs (PWM0 to PWM6).
To enable the alternative functions of Ports 1, 3 and 5, the
port bit latch of its associated SFR must contain a logic 1.
Each port consists of a latch (SFRs P0, P1, P3 and P5), an
output driver and an input buffer.
7.2 Port configurations
1. Open-drain quasi-bidirectional I/O with n-channel
pull-down (see Fig.6). Use as an output requires the
connection of an external pull-up resistor. Use as an
input requires to write a logic 1 to the port latch before
reading the port line.
2. Push-pull; gives drive capability of the output in both
polarities, see Fig.7.
handbook, halfpage
Q
from port latch
input data
read port pin
n
INPUT
BUFFER
I/O pin
MGK547
handbook, halfpage
Q
from port latch
strong pull-up
+5 V
p1
n
output pin
MGM679
Fig.6 Open-drain port.
Fig.7 Push-pull port.
1999 Mar 10
12