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TDA8793 Datasheet, PDF (8/20 Pages) NXP Semiconductors – 8-bit, low-power, 3 V, 100 Msps Analog-to-Digital Converter ADC
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Philips Semiconductors
8-bit, low-power, 3 V, 100 Msps
Analog-to-Digital Converter (ADC)
Preliminary specification
TDA8793
SYMBOL
PARAMETER
CONDITIONS
MIN.
Analog signal processing; note 3; see Figs 4, 5, 6 and 7
INL
DNL
S/N
BW(−3dB)
THD
Hfund(FS)
HD2(FS)
HD3(FS)
SFDR
EB
integral non-linearity
ramp input; fCLK = 2 MHz; −
VCCA = VCCD = 3 V
differential non-linearity
ramp input; fCLK = 2 MHz; −
VCCA = VCCD = 3 V
signal-to-noise ratio (full scale)
without harmonics;
fCLK = 100 MHz
fi = 20 MHz
42
fi = 50 MHz
−
−3 dB analog bandwidth
−
total harmonics distortion
fi = 20 MHz
−
fi = 50 MHz
−
full scale fundamental harmonics fCLK = 100 MHz
fi = 20 MHz
−
fi = 50 MHz
−
second harmonic distortion (full
scale) all components included
differential inputs;
fCLK = 100 MHz
fi = 20 MHz
−
fi = 50 MHz
−
single-ended input;
fCLK = 100 MHz
fi = 20 MHz
−
fi = 50 MHz
−
third harmonic distortion (full scale) differential inputs;
all components included
fCLK = 100 MHz
fi = 20 MHz
−
fi = 50 MHz
−
single-ended input;
fCLK = 100 MHz
fi = 20 MHz
−
fi = 50 MHz
−
spurious free dynamic range
fCLK = 100 MHz
fi = 20 MHz
−
fi = 50 MHz
−
effective bits
fCLK = 100 MHz; note 4
fi = 20 MHz
7.0
fi = 50 MHz
−
Data timing; fCLK = 100 MHz; CL = 10 pF; see Fig.8
tds
sampling delay
−
th
output hold time
3
td
output delay time
−
TYP. MAX. UNIT
±0.8 tbf
LSB
±0.25 tbf
LSB
45
−
45
−
350 −
−56 −
−52 −
−
0
−
0
dB
dB
MHz
dB
dB
dB
dB
66
−
dB
57
−
dB
66
−
dB
55
−
dB
64
−
dB
61
−
dB
64
−
dB
59
−
dB
dB
57
−
dB
54
−
dB
bits
7.4
−
bits
7.2
−
bits
−
1.5
ns
−
−
ns
5
8
ns
1999 Oct 06
8
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