TDA8792 Datasheet, PDF (8/20 Pages) NXP Semiconductors – 3.3 V, 25 MHz 8-bit analog-to-digital converter ADC

Philips Semiconductors
3.3 V, 25 MHz 8-bit
analog-to-digital converter (ADC)
Product specification
TDA8792
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
EFFECTIVE BITS; see Figs 6 and 11; note 4
EB
effective bits
DIFFERENTIAL GAIN; see note 5
f_clk = 25 MHz
f_i = 2.0 MHz
f_i = 4.43 MHz
f_i = 7.5 MHz
f_i = 10 MHz
−
7.4 −
bits
−
7.3 −
bits
−
7.2 −
bits
−
7.0 −
bits
G_diff
differential gain
f_clk = 25 MHz;
−
PAL modulated ramp
1.5 −
%
DIFFERENTIAL PHASE; see note 5
ϕ_diff
differential phase
f_clk = 25 MHz;
−
PAL modulated ramp
0.5 −
deg
Timing (f_clk = 25 MHz); see Fig.3 and note 6
t_ds
sampling delay time
t_h
output hold time
t_d
output delay time
−
−
2
ns
6
−
−
ns
8
13
25
ns
3-state output delay times; see Fig.4
t_dZH
enable HIGH
t_dZL
enable LOW
t_dHZ
disable HIGH
t_dLZ
disable LOW
−
17
28
ns
−
22
30
ns
−
20
28
ns
−
22
30
ns
Standby mode output delay times
t_dSTBLH
t_dSTBHL
standby (LOW-to-HIGH transition)
start-up (HIGH-to-LOW transition)
−
−
200 ns
−
−
note 7 ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. The analog bandwidth is defined as the maximum full-scale input sine wave frequency which can be applied to the
device. No glitches greater than 8 LSBs are observed in the reconstructed signal neither is there any significant
attenuation.
3. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
5. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a
digital-to-analog converter.
6. Output data acquisition: the output data is available after the maximum delay time of t_d. In the event of 25 MHz clock
operation, the hardware design must be taken into account the t_d and t_h limits with respect to the input characteristics
of the acquisition circuit.
7. Maximum value standby mode start-up output delay time (HIGH-to-LOW transition): 100 + -f-_c---_l-7_k---(-0-M--0---H0----z---)- .
1996 Feb 21
8