TDA8790 Datasheet, PDF (8/20 Pages) NXP Semiconductors – 8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter

Philips Semiconductors
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
Product specification
TDA8790
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
SIGNAL-TO-NOISE RATIO; see Fig.9; note 6
S/N
signal-to-noise ratio (full scale)
without harmonics;
−
f_clk = 40 MHz;
f_i = 4.43 MHz
EFFECTIVE BITS; see Fig.9; note 6
EB
effective bits
f_clk = 40 MHz
f_i = 300 kHz
−
f_i = 4.43 MHz
−
DIFFERENTIAL GAIN; see note 7
G_diff
differential gain
f_clk = 40 MHz;
−
PAL modulated ramp
47
−
dB
7.8 −
bits
7.3 −
bits
1.5 −
%
DIFFERENTIAL PHASE; see note 7
ϕ_diff
differential phase
f_clk = 40 MHz;
−
PAL modulated ramp
0.25 −
deg
Timing (f_clk = 40 MHz; C_L = 20 pF); see Fig.4; note 8
t_ds
sampling delay time
t_h
output hold time
t_d
output delay time
V_DDO = 4.75 V
V_DDO = 3.15 V
V_DDO = 2.7 V
−
−
5
ns
5
−
−
ns
8
12
15
ns
8
17
20
ns
8
18
21
ns
3-state sleep mode delay times; see Fig.5
t_dZH
enable HIGH
t_dZL
enable LOW
t_dHZ
disable HIGH
t_dLZ
disable LOW
−
14
18
ns
−
16
20
ns
−
16
20
ns
−
14
18
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Analog input voltages producing code 0 up to and including 256:
a) V_osB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (V_RB) at T_amb = 25 °C.
b) V_osT (voltage offset TOP) is the difference between V_RT (reference voltage TOP) and the analog input which
produces data outputs equal to 256 at T_amb = 25 °C.
1996 Feb 21
8