TDA8790 Datasheet, PDF (7/20 Pages) NXP Semiconductors – 8-bit, 40 Msps 2.7 to 5.5 V universal analog-to-digital converter

Philips Semiconductors
8-bit, 40 Msps 2.7 to 5.5 V universal
analog-to-digital converter
Product specification
TDA8790
SYMBOL
PARAMETER
R_LAD
TC_RLAD
resistor ladder
temperature coefficient of the
resistor ladder
V_osB
V_osT
V_i(p-p)
offset voltage BOTTOM
offset voltage TOP
analog input voltage (peak-to-peak
value)
CONDITIONS
note 2
note 2
note 3
MIN.
−
−
−
−
−
1.4
TYP.
2.2
1 860
4 092
170
170
1.76
MAX.
−
−
−
−
−
2.4
Outputs
DIGITAL OUTPUTS D7 TO D0 (REFERENCED TO V_SSD)
V_OL
LOW level output voltage
I_O = 1 mA
V_OH
HIGH level output voltage
I_O = −1 mA
I_OZ
output current in 3-state mode
0.4 V < V_O < V_DDO
Switching characteristics
0
−
V_DDO − 0.5 −
−20
−
0.5
V_DDO
+20
CLOCK INPUT CLK; see Fig.4; note 1
f_clk(max)
t_CPH
t_CPL
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
Analog signal processing
40
−
−
9
−
−
9
−
−
LINEARITY
INL
integral non-linearity
DNL
differential non-linearity
f_clk = 40 MHz; ramp input; −
see Fig.6
f_clk = 40 MHz; ramp input; −
see Fig.7
±0.5 ±0.75
±0.25 ±0.5
BANDWIDTH (f_clk = 40 MHz)
B
analog bandwidth
full-scale sine wave;
−
note 4
75% full-scale sine wave; −
note 4
50% full-scale sine wave; −
note 4
small signal at mid scale; −
V_i = ±10 LSB at
code 128; note 4
10
−
13
−
20
−
350 −
INPUT SET RESPONSE (f_clk = 40 MHz; see Fig.8; note 5)
t_STLH
analog input settling time
LOW-to-HIGH
full-scale square wave
−
t_STHL
analog input settling time
HIGH-to-LOW
full-scale square wave
−
3
5
3
5
HARMONICS; (f_clk = 40 MHZ; see Fig.9; note 6)
THD
total harmonic distortion
f_i = 4.43 MHz
−
−50 −
UNIT
kΩ
ppm
mΩ/K
mV
mV
V
V
V
µA
MHz
ns
ns
LSB
LSB
MHz
MHz
MHz
MHz
ns
ns
dB
1996 Feb 21
7