TDA8354Q Datasheet, PDF(8/16 Page) NXP Semiconductors – Full bridge current driven vertical deflection output circuit in LVDMOS

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TDA8354Q Datasheet, PDF (8/16 Pages) NXP Semiconductors – Full bridge current driven vertical deflection output circuit in LVDMOS

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Philips Semiconductors

Full bridge current driven vertical deï¬ection

output circuit in LVDMOS

Preliminary speciï¬cation

TDA8354Q

SYMBOL

âGi(T)

PSRR

PARAMETER

current gain drift as function of

temperature

power supply rejection ratio

CONDITIONS

note 6

MIN. TYP. MAX. UNIT

10â4

Input stage

Ii(bias)

Ii(diff)(p-p)

signal bias current

differential mode input current

(peak-to-peak value) pin 11 or 12

Vi(diff)

Vi(cm)

differential mode input voltage

common mode input voltage

Flyback switch

note 7

Ii(diff) = 500 ÂµA

Ii(bias) = 330 ÂµA

330

500

ÂµA

500

600

ÂµA

0.75 â

0.95 1.15 1.35 V

Io(Vï¬b)

Vloss

output peak current

voltage loss (Vï¬b â Vo(A))

Guard circuit

t < 1.5 ms

Io = +1.6 A

Â±1.6 A

Io(guard)

output current

Vo(guard)

output voltage on pin 1

allowable voltage on pin 1

not active;

ÂµA

Vo(guard) = 0 V

active; Vo(guard) = 4.5 V 1

2.5

Io(guard) = 100 ÂµA

maximum leakage

current = 10 ÂµA

Notes

1. At Tj = 125 Â°C. The temperature coefficient of Vloss has a positive sign.

2. The linearity error is measured without S correction and based on the same measurement principle as performed on

the screen. The measuring method is as follows:

Divide the output signal into 22 equal time parts ranging from 1 to 22 inclusive. Measure the value of the voltage

across RM of two succeeding parts called one block (a) starting with part 2 and 3 (block 1) and ending with

part 20 and 21 (block 10). Thus parts 1 and 22 are unused. The equations for linearity error for adjacent blocks

(LEAB) and not adjacent blocks (LENAB) are given below:

LEAB = a----k----â---a-a---a--(-v-k---+----1--)-

LENAB = a----m----a---xa----âa---v-a----m----i-n-

3. Vo(A) + Vo(B) = VP. At the start of the scan this equation is one diode voltage less.

4. The V value within formulae relates to voltages at or between relative pin numbers, i.e. V9 to 5/V3 to 5 = voltage value

across pins 9 and 5 divided by voltage value across pins 3 and 5.

5. V2 to 5 AC short-circuited.

6. At V(ripple) = 500 mV (eff) at VP; measured across RM; f(ripple) = 50 Hz â 1 kHz.

7. Ii(bias) + Ii(diff) â¤ 800 ÂµA and Ii(bias) â Ii(diff) â¥ 50 ÂµA per pin.

1998 Sep 03

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