TDA8354Q Datasheet, PDF (6/16 Pages) NXP Semiconductors – Full bridge current driven vertical deflection output circuit in LVDMOS

Philips Semiconductors
Full bridge current driven vertical deflection
output circuit in LVDMOS
Preliminary specification
TDA8354Q
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN. MAX. UNIT
DC supply
V_P
supply voltage
V_flb
flyback supply voltage
Vertical circuit
I_o(p-p)
V_o(A)
V_o(B)
I_{1,2,3,11,12,13}
output current (peak-to-peak value)
output voltage (pin 9)
output voltage (pin 5)
current into or out of
pins 1 to 3 and 11 to 13
V_{1,2,3,11,12,13} peak voltage on pins 1 to 3 and 11 to 13
Flyback switch
I_o(Vflb)
peak output current
Thermal data (in accordance with IEC 747-1)
T_stg
T_amb
T_j
storage temperature
operating ambient temperature
junction temperature
Miscellaneous
t_sc
short-circuiting time
I_i/o
current into any pin
current out of any pin
V_ESD
electrostatic handling
note 1
note 2
note 3
+1.5 × V_P(max); note 4
−1.5 × V_P(max); note 4
note 5
note 6
−
−
−
−
−
−20
−0.5
−
−55
−25
−
−
−
−200
−
−
18
V
68
V
3.2
A
68
V
V_P
V
+20
mA
V_P
V
±1.6
A
+150 °C
+75
°C
150
°C
1
h
+200 mA
−
mA
±300 V
±2000 V
Notes
1. When the pin voltage exceeds 70 V the device behaves like a power zener diode thus limiting the voltage.
2. Internally limited by thermal protection; switching point ≈170 °C.
3. Up to V_P = 18 V.
4. At T_j(max).
5. Machine model: equivalent to discharge a 200 pF capacitor through a 0 Ω series resistor. Except pin 7: ±250 V.
6. Human body model: equivalent to discharge a 100 pF capacitor through a 1.5 kΩ series resistor. Except pin 7:
±1500 V.
1998 Sep 03
6