SSTU32865 Datasheet, PDF (8/29 Pages) NXP Semiconductors – 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

Philips Semiconductors
SSTU32865
1.8 V DDR registered buffer with parity
7. Functional description
7.1 Function table
Table 3: Function table (each flip-flop)
Inputs
RESET DCS0 DCS1 CSGATEEN CK
H
L
L
X
↑
H
L
L
X
↑
H
L
L
X
L or H
H
L
H
X
↑
H
L
H
X
↑
H
L
H
X
L or H
H
H
L
X
↑
H
H
L
X
↑
H
H
L
X
L or H
H
H
H
L
↑
H
H
H
L
↑
H
H
H
L
L or H
H
H
H
H
↑
H
H
H
H
↑
H
H
H
H
L or H
L
X or
X or X or floating X or
floating floating
floating
[1] Q₀ is the previous state of the associated output.
Outputs ^[1]
CK Dn, DODTn, Qn QCS0 QCS1 QODTn,
DCKEn
QCKEn
↓
L
L
L
L
L
↓
H
H
L
L
H
L or H
X
Q₀
Q₀
Q₀
Q₀
↓
L
L
L
H
L
↓
H
H
L
H
H
L or H
X
Q₀
Q₀
Q₀
Q₀
↓
L
L
H
L
L
↓
H
H
H
L
H
L or H
X
Q₀
Q₀
Q₀
Q₀
↓
L
L
H
H
L
↓
H
H
H
H
H
L or H
X
Q₀
Q₀
Q₀
Q₀
↓
L
Q₀
H
H
L
↓
H
Q₀
H
H
H
L or H
X
Q₀
Q₀
Q₀
Q₀
X or X or floating L
L
L
L
floating
Table 4: Parity and standby function table
Inputs
RESET
DCS0
DCS1
CK
CK
H
L
H
↑
↓
H
L
H
↑
↓
H
L
H
↑
↓
H
L
H
↑
↓
H
H
L
↑
↓
H
H
L
↑
↓
H
H
L
↑
↓
H
H
L
↑
↓
H
H
H
↑
↓
H
X
X
L or H
L or H
L
X or floating X or floating X or floating X or floating
∑ of inputs = H
(D0 to D21)
even
odd
even
odd
even
odd
even
odd
X
X
X or floating
PARIN ^[1]
Output
PTYERR ^{[2] [3]}
L
L
H
H
L
L
H
H
X
X
X or floating
H
L
L
H
H
L
L
H
PTYERR₀
PTYERR₀
H
[1] PARIN arrives one clock cycle after the data to which it applies. All Dn inputs must be driven to a known state for parity to be calculated
correctly.
9397 750 13799
Product data sheet
Rev. 02 — 28 September 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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