SSTU32865 Datasheet, PDF (23/29 Pages) NXP Semiconductors – 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM

Philips Semiconductors
12. Package outline
SSTU32865
1.8 V DDR registered buffer with parity
TFBGA160: plastic thin fine-pitch ball grid array package; 160 balls; body 9 x 13 x 0.8 mm
SOT802-1
D
BA
ball A1
index area
E
A ^{A2 A1}
detail X
e1
e
b
1/2e
∅v M C A B
∅w M C
y1 _C
V
U
T
R
e
P
N
M
L
K
J
e2
H
G
1/2e
F
E
D
C
B
A
ball A1
index area
1 3 5 7 9 11
2 4 6 8 10 12
0
5
DIMENSIONS (mm are the original dimensions)
scale
UNIT
A
max.
A₁
A₂
b
D
E
e
e₁
e₂
v
w
y
mm
1.2
0.35 0.85 0.45
0.25 0.75 0.35
9.1
8.9
13.1
12.9
0.65
7.15 11.05 0.15
0.08
0.1
10 mm
y₁
0.1
C
y
X
OUTLINE
VERSION
IEC
SOT802-1
---
REFERENCES
JEDEC
JEITA
---
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EUROPEAN
PROJECTION
ISSUE DATE
03-01-29
Fig 22. Package outline SOT802-1 (TFBGA160)
9397 750 13799
Product data sheet
Rev. 02 — 28 September 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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