83C749 Datasheet, PDF (8/22 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
Preliminary specification
83C749/87C749
Pulse Width Modulation Output (P0.4)
The PWM outputs pulses of programmable length and interval. The
repetition frequency is defined by an 8-bit prescaler which generates
the clock for the counter. The prescaler register is PWMP. The
prescaler and counter are not associated with any other timer. The
8-bit counter counts modulo 255, that is from 0 to 254 inclusive. The
value of the 8-bit counter is compared to the contents of a compare
register, PWM. When the counter value matches the contents of this
register, the output of the PWM is set high. When the counter reaches
zero, the output of the PWM is set low. The pulse width ratio (duty
cycle) is defined by the contents of the compare register and is in the
range of 0 to 1 programmed in increments of 1/255. The PWM output
can be set to be continuously high by loading the compare register
with 0 and the output can be set to be continuously low by loading the
compare register with 255. The PWM output is enabled by a bit in a
special function register, PWENA. When enabled, the pin output is
driven with a fully active pull-up. That is, when the output is high, a
strong pull-up is continuously applied. When disabled, the pin
functions as a normal bidirectional I/O pin, however, the counter
remains active.
The PWM function is disabled during RESET and remains disabled
after reset is removed until re-enabled by software. The PWM output
is high during power down and idle. The counter is disabled during
idle. The repetition frequency of the PWM is given by:
f_PWM = f_OSC / 2 (1 + PWMP) 255
The low/high ratio of the PWM signal is PWM / (255 – PWM) for
PWM not equal to 255. For PWM = 255, the output is always low.
The repetition frequency range is 92Hz to 23.5kHz for an oscillator
frequency of 12MHz.
An interrupt will be asserted upon PWM counter overflow if the
interrupt is not masked off.
The PWM output is an alternative function of P0.4. In order to use
this port as a bidirectional I/O port, the PWM output must be
disabled by clearing the enable/disable bit in PWENA. In this case,
the PWM subsystem can be used as an interval timer by enabling
the PWM interrupt.
Special Function Register Addresses
Special function registers for the 8XC749 are identical to those of
the 80C51, except for the changes listed below:
80C51 special function registers not present in the 8XC749 are
TMOD (89), P2 (A0) and IP (B8). Additional special function
registers are ADCON (A0), ADAT (84), PWM (8E), PWMP (8F), and
PWENA (FE).
A/D Converter
The analog input circuitry consists of a 5-input analog multiplexer and
an A to D converter with 8-bit resolution. The conversion takes 40
machine cycles, i.e., 40µs at 12MHz oscillator frequency. The A/D
converter is controlled using the ADCON control register. Input
channels are selected by the analog multiplexer through ADCON
register bits 0–2.
The 83C749 contains a five-channel multiplexed 8-bit A/D converter.
The conversion requires 40 machine cycles (40µs at 12MHz
oscillator frequency).
The A/D converter is controlled by the A/D control register, ADCON.
Input channels are selected by the analog multiplexer by bits
ADCON.0 through ADCON.2. The ADCON register is not bit
addressable.
ADCON Register
MSB
X
X
ENADC
ADCI
ADCS
AADR2
AADR1
LSB
AADR0
ADCI
0
0
1
1
ADCS
0
1
0
1
Operation
ADC not busy, a conversion can be started.
ADC busy, start of a new conversion is blocked.
Conversion completed, start of a new conversion is
blocked.
Not possible.
ADDR2
0
0
0
0
1
INPUT CHANNEL SELECTION
ADDR1
ADDR0
0
0
0
1
1
0
1
1
0
0
INPUT PIN
P1.0
P1.1
P1.2
P1.3
P1.4
Position
ADCON.5
ADCON.4
ADCON.3
ADCON.2
ADCON.1
ADCON.0
Symbol
ENADC
ADCI
ADCS
AADR2
AADR1
AADR0
Function
Enable A/D function when ENADC = 1. Reset
forces ENADC = 0.
ADC interrupt flag. This flag is set when an
ADC conversion is complete. If IE.6 = 1, an
interrupt is requested when ADCI = 1. The
ADCI flag is cleared when conversion data is
read. This flag is read only.
ADC start. Setting this bit starts an A/D
conversion. Once set, ADCS remains high
throughout the conversion cycle. On
completion of the conversion, it is reset just
before the ADCI interrupt flag is cleared.
ADCS cannot be reset by software. ADCS
should not be used to monitor the A/D
converter status. ADCI should be used for this
purpose.
Analog input select.
Analog input select.
Analog input select. This binary coded
address selects one of the five analog input
port pins of P1 to be input to the converter. It
can only be changed when ADCI and ADCS
are both low. AADR2 is the most significant
bit.
The completion of the 8-bit ADC conversion is flagged by ADCI in
the ADCON register, and the result is stored in the special function
register ADAT.
An ADC conversion in progress is unaffected by an ADC start. The
result of a completed conversion remains unaffected provided ADCI
remains at a logic 1. While ADCS is a logic 1 or ADCI is a logic 1, a
new ADC START will be blocked and consequently lost. An ADC
conversion in progress is aborted when the idle or power-down
mode is entered. The result of a completed conversion (ADCI = logic
1) remains unaffected when entering the idle mode. See Figure 2 for
an A/D input equivalent circuit.
The analog input pins ADC0-ADC4 may be used as digital inputs
and outputs when the A/D converter is disabled by a 0 in the
ENADC bit in ADCON. When the A/D is enabled, the analog input
channel that is selected by the ADDR2-ADDR0 bits in ADCON
cannot be used as a digital input. Reading the selected A/D channel
as a digital input will always return a 1. The unselected A/D inputs
1998 Apr 23
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