83C749 Datasheet, PDF (7/22 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
Preliminary specification
83C749/87C749
Port 1
Port 1 is an 8-bit bidirectional I/O port whose structure is identical to
the 80C51, but also includes alternate input functions on all pins.
The alternate pin functions for port 1 are:
P1.0-P1.4 - ADC0-ADC4 - A/D converter analog inputs
P1.5 INT0 - external interrupt 0 input
P1.6 INT1 - external interrupt 1 input
P1.7 - T0 - timer 0 external input
If the alternate functions INT0, INT1, or T0 are not being used, these
pins may be used as standard I/O ports. It is necessary to connect
AV_CC and AV_SS to V_CC and V_SS, respectively, in order to use P1.5,
P1.6, and P1.7 pins as standard I/O pins. When the A/D converter is
enabled, the analog channel connected to the A/D may not be used
as a digital input; however, the remaining analog inputs may be used
as digital inputs. They may not be used as digital outputs. While the
A/D is enabled, the analog inputs are floating.
Port 3
Port 3 is an 8-bit bidirectional I/O port whose structure is identical to
the 80C51. Note that the alternate functions associated with port 3
of the 80C51 have been moved to port 1 of the 83C749 (as
applicable). See Figure 1 for port bit configurations.
Counter/Timer Subsystem
The 8XC749 has one counter/timer called timer/counter 0. Its
operation is similar to mode 2 operation on the 80C51, but is
extended to 16 bits with 16 bits of autoload. The controls for this
counter are centralized in a single register called TCON.
Timer I Implementation
Timer I is clocked once per machine cycle, which is the oscillator
frequency divided by 12. The timer operation is enabled by setting
the TIRUN bit (bit 4) in the I2CFG register. Writing a 0 into the
TIRUN bit will stop and clear the timer. The timer is 10 bits wide, and
when it reaches the terminal count of 1024, it carries out and sets
the Timer I interrupt flag. An interrupt will occur if the Timer I
interrupt is enabled by bit ETI (bit 4) of the Interrupt Enable (IE)
register, and global interrupts are enabled by bit EA (bit 7) of the
same IE register.
The vector address for the Timer I interrupt is 1Bhex, and the
interrupt service routine must start at this address. As with all 8051
family microcontrollers, only the Program Counter is pushed onto
the stack upon interrupt (other registers that are used both by the
interrupt service routine and elsewhere must be explicitly saved).
The Timer I interrupt flag is cleared by setting the CKRTI bit (bit 5 of
the I1CFG register. For more information, see application note
AN427.
Interrupt Subsystem—Fixed Priority
The IP register and the 2-level interrupt system of the 80C51 are
eliminated. The interrupt structure is a seven-source, one-level
interrupt system similar to the 8XC751. Simultaneous interrupt
conditions are resolved by a single-level, fixed priority as follows:
Highest priority: Pin INT0
Counter/timer flag 0
Pin INT1
PWM
Timer I
Lowest priority: ADC
The vector addresses are as follows:
Source
INT0
TF0
INT1
TIMER I
ADC
PWM
Vector Address
0003H
000BH
0013H
001BH
002BH
0033H
Interrupt Control Registers
The 80C51 interrupt enable register is modified to take into account
the different interrupt sources of the 8XC749.
Interrupt Enable Register
MSB
LSB
EA
EAD
ETI
—
EPWM EX1
ET0
EX0
Position Symbol
IE.7
EA
IE.6
EAD
IE.5
ETI
IE.4
—
IE.3
EPWM
IE.2
EX1
IE.1
ET0
IE.0
EX0
Function
Global interrupt disable when EA = 0
A/D conversion complete
Timer I
PWM counter overflow
External interrupt 1
Timer 0 overflow
External interrupt 0
READ
LATCH
INT. BUS
WRITE TO
LATCH
ALTERNATE
OUTPUT
FUNCTION
D
Q
P1.X
LATCH
CL
Q
V_DD
INTERNAL
PULL-UP
P1.X
PIN
READ
LATCH
INT. BUS
WRITE TO
LATCH
ALTERNATE
OUTPUT
FUNCTION
D
Q
P0.X
LATCH
CL
Q
P0.X
PIN
READ
PIN
1998 Apr 23
ALTERNATE INPUT
FUNCTION
READ
PIN
ALTERNATE INPUT
FUNCTION
Figure 1. Port Bit Latches and I/O Buffers
7
SU00306