80C562 Datasheet, PDF (8/20 Pages) NXP Semiconductors – Single-chip 8-bit microcontroller

Philips Semiconductors
Single-chip 8-bit microcontroller
Product specification
80C562/83C562
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
Analog Inputs
AV_DD
AI_DD
AI_ID
Analog supply voltage:
PCB8XC562
PCF8XC562
PCA8XC562
Analog supply current: operating:
Idle mode:
PCB8XC562
PCF8XC562
PCA8XC562
AV_DD = V_DD±0.2V
4.0
AV_DD = V_DD±0.2V
4.0
AV_DD = V_DD±0.2V
4.5
Port 5 = 0 to AV_DD
6.0
V
6.0
V
5.5
V
1.2
mA
50
µA
50
µA
100
µA
AI_PD
Power-down mode:
PCB8XC562
PCF8XC562
PCA8XC562
2V < AV_PD < AV_DD max
50
µA
50
µA
100
µA
AV_IN
Analog input voltage
AV_SS–0.2
AV_DD+0.2
V
AV_REF
Reference voltage:
AV_REF–
AV_REF+
AV_SS–0.2
V
AV_DD+0.2
V
R_REF
Resistance between AV_REF+ and AV_REF–
5
25
kΩ
C_IA
Analog input capacitance
15
pF
t_ADS
Sampling time
6t_CY
µs
t_ADC
Conversion time (including sampling time)
24t_CY
µs
DL_e
Differential non-linearity^{8, 9, 10}
±1
LSB
IL_e
Integral non-linearity^{8, 11}
±1
LSB
OS_e
Offset error^{8, 12}
±1
LSB
G_e
Gain error^{8, 13}
0.4
%
M_CTC
Channel to channel matching
±1
LSB
C_t
Crosstalk between inputs of port 5¹⁴
0–100kHz
–60
dB
NOTES:
1. See Figures 8 through 12 for I_DD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t_r = t_f = 10ns; V_IL = V_SS + 0.5V;
V_IH = V_DD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = V_DD; STADC = V_SS.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t_r = t_f = 10ns; V_IL = V_SS + 0.5V;
V_IH = V_DD – 0.5V; XTAL2 not connected; Port 0 = EW = V_DD; EA = RST = STADC = V_SS.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = V_DD;
EA = RST = STADC = XTAL1 = V_SS.
5. Pins of ports 1, 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V_IN is approximately 2V.
6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V_OLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I_OL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
7. Capacitive loading on ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily fall below the 0.9V_DD specification when the
address bits are stabilizing.
8. Conditions: AV_REF– = 0V; AV_DD = 5.0V, AV_REF+ = 5.12V. ADC is monotonic with no missing codes.
9. The differential non-linearity (DL_e) is the difference between the actual step width and the ideal step width. (See Figure 1.)
10. The ADC is monotonic; there are no missing codes.
11. The integral non-linearity (IL_e) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset error. (See Figure 1.)
12. The offset error (OS_e) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
a straight line which fits the ideal transfer curve. (See Figure 1.)
13. The gain error (G_e) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)
14. This should be considered when both analog and digital signals are simultaneously input to port 5.
1992 Jan 08
8