80C562 Datasheet, PDF (5/20 Pages) NXP Semiconductors – Single-chip 8-bit microcontroller

Philips Semiconductors
Single-chip 8-bit microcontroller
Product specification
80C562/83C562
PIN DESCRIPTION
MNEMONIC PIN NO. TYPE
NAME AND FUNCTION
V_DD
STADC
2
I Digital Power Supply: +5V power supply pin during normal operation, idle and power-down mode.
3
I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started
by software).
PWM0
4
O Pulse Width Modulation: Output 0.
PWM1
5
O Pulse Width Modulation: Output 1.
EW
6
I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
P0.0–P0.7
57–50
I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memory. In this application it uses strong internal
pull-ups when emitting 1s.
P1.0–P1.7
16–23
16–23
16–19
20
21
I/O Port 1: 8-bit I/O port. Alternate functions include:
I/O
(P1.0–P1.7): Quasi-bidirectional port pins.
I/O
CT0I–CT3I (P1.0–P1.3): Capture timer input signals for timer T2.
I
T2 (P1.4): T2 event input
I
RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
P2.0–P2.7
39–46
I/O Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08–A15).
P3.0–P3.7
24–31
24
25
26
27
28
29
30
31
I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
RxD(P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt.
INT1 (P3.3): External interrupt.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
P4.0–P4.7
7–14
7–12
13, 14
I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
O
CMSR0–CMSR5 (P4.0–P4.5): Timer T2 compare and set/reset outputs on a match with timer T2.
O
CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
P5.0–P5.7
68–62,
1
I Port 5: 8-bit input port.
ADC0–ADC7 (P5.0–P5.7): Alternate function: Eight input channels to ADC.
RST
15
I/O Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3 overflows.
XTAL1
35
I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock
generator. Receives the external clock signal when an external oscillator is used.
XTAL2
34
O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open–circuit when an
external clock is used.
V_SS
PSEN
36, 37
47
I Digital ground.
O Program Store Enable: Active-low read strobe to external program memory.
ALE
48
O Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is
activated every six oscillator periods. During an external data memory access, one ALE pulse is
skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external
pull-up.
EA
49
I External Access: When EA is held at TTL level high, the CPU executes out of the internal program
ROM provided the program counter is less than 8192. When EA is held at TTL low level, the CPU
executes out of external program memory. EA is not allowed to float.
AV_REF–
58
I Analog to Digital Conversion Reference Resistor: Low-end.
AV_REF+
59
I Analog to Digital Conversion Reference Resistor: High-end.
AV_SS
60
I Analog Ground
AV_DD
61
I Analog Power Supply
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V_DD +0.5V or V_SS – 0.5V,
respectively.
1992 Jan 08
5