74HC112 Datasheet, PDF (8/15 Pages) NXP Semiconductors – Dual JK flip-flop with set and reset; negative-edge trigger

Philips Semiconductors
Dual JK flip-flop with set and reset;
negative-edge trigger
Product specification
74HC/HCT112
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF
T_amb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
74HCT
+25
−40 to +85
−40 to +125
UNIT
V_CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
t_PHL/ t_PLH
propagation delay
nCP to nQ
21 35
t_PHL/ t_PLH
propagation delay
nCP to nQ
23 40
t_PHL/ t_PLH
propagation delay
nR_D to nQ, nQ
22 37
t_PHL/ t_PLH
propagation delay
nS_D to nQ, nQ
18 32
t_THL/ t_TLH output transition time
7 15
t_W
clock pulse width
HIGH or LOW
16 8
t_W
set or reset pulse width
LOW
18
10
t_rem
removal time
nR_D to nCP
t_rem
removal time
nS_D to nCP
t_su
set-up time
nJ, nK to nCP
20 11
20 −8
16 7
t_h
hold time
nJ, nK to nCP
0 −7
f_max
maximum clock pulse
frequency
30
64
44
50
46
40
19
20
23
25
25
20
0
24
53 ns 4.5 Fig.6
60 ns 4.5 Fig.6
56 ns 4.5 Fig.7
48 ns 4.5 Fig.7
22 ns 4.5 Fig.6
24
ns 4.5 Fig.6
27
ns 4.5 Fig.7
30
ns 4.5 Fig.7
30
ns 4.5 Fig.7
24
ns 4.5 Fig.6
0
ns 4.5 Fig.6
20
MHz 4.5 Fig.6
1998 Jun 10
8