74HC112 Datasheet, PDF (4/15 Pages) NXP Semiconductors – Dual JK flip-flop with set and reset; negative-edge trigger

Philips Semiconductors
Dual JK flip-flop with set and reset;
negative-edge trigger
Product specification
74HC/HCT112
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
asynchronous set
asynchronous reset
undetermined
toggle
load “0” (reset)
load “1” (set)
hold “no change”
INPUTS
nS_D nR_D nCP nJ nK
L
HXXX
H
LXXX
L
LXXX
H
H↓h h
H
H↓
l
h
H
H↓ h
l
H
H↓
l
l
OUTPUTS
nQ nQ
H
L
L
H
H
L
q
q
L
H
H
L
q
q
Note
1. If nS_D and nR_D simultaneously go from LOW to HIGH, the output states will
be unpredictable.
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP
transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP
transition
q = lower case letters indicate the state of the referenced output one set-up
time prior to the HIGH-to-LOW CP transition
X = don’t care
↓ = HIGH-to-LOW CP transition
1998 Jun 10
Fig.5 Logic diagram (one flip-flop).
4