P8XCE560 Datasheet, PDF (70/84 Pages) NXP Semiconductors – 80C51 Central Processing Unit (CPU)

Philips Semiconductors
8-bit microcontroller
Product specification
P8xCE560
handbook, full pagewidth
XTAL1
INPUT
one machine cycle
one machine cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
dotted lines
are valid when
RD or WR are
active
ALE
PSEN
only active
during a read
from external
RD
data memory
only active
during a write
to external
WR
data memory
external
program
memory
fetch
BUS
inst.
(PORT 0) in
PORT 2
address
inst.
A0 - A7
in
address A8 - A15
address
inst.
A0 - A7
in
address A8 - A15
address
inst.
A0 - A7
in
address A8 - A15
address
A0 - A7
address A8 - A15
read or
write of
external data
memory
BUS
inst.
(PORT 0) in
PORT 2
address
A0 - A7
inst.
address
in
A0 - A7
address A8 - A15
data output or data input
address A8 - A15 or Port 2 out
address
A0 - A7
address A8 - A15
PORT
OUTPUT
PORT
INPUT
SERIAL
PORT
CLOCK
old data
new data
sampling time of I/O port pins during input (including INT0 and INT1)
MGA180
The Port 5 input buffers have a maximum propagation delay of 300 ns.
As a result Port 5 sample time begins 300 ns before state S5 and ends when S5 has finished.
Fig.26 Instruction cycle timing.
1997 Aug 01
70